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updated documentation

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stnolting 2020-09-01 22:03:55 +02:00
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README.md
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@ -107,7 +107,6 @@ The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and
### Non RISC-V-Compliant Issues
* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
* `mcause` CSR is read-only
* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)

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docs/NEORV32.pdf
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