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DEVNULL simulation output now also dumps full 32-bit written data in hex form

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This commit is contained in:
stnolting 2020-06-28 22:15:55 +02:00
parent b781c9d4f5
commit 462a91b384
4 changed files with 61 additions and 17 deletions
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6
.ci/hw_check.sh
View file

@ -59,15 +59,17 @@ touch neorv32.testbench_uart.out
chmod 777 neorv32.testbench_uart.out
touch neorv32.devnull.out
chmod 777 neorv32.devnull.out
touch neorv32.devnull.data.out
chmod 777 neorv32.devnull.data.out
# Run simulation
ghdl -e --work=neorv32 neorv32_tb
ghdl -r --work=neorv32 neorv32_tb --stop-time=5ms --ieee-asserts=disable --assert-level=error
# Check output
echo "Checking NEORV32.DEVNULL output. Should contain:"; cat $homedir/check_reference.out
echo "Checking NEORV32.DEVNULL text output. Should contain:"; cat $homedir/check_reference.out
echo ""
echo "Checking NEORV32.DEVNULL output. NEORV32.DEVNULL output is:"
echo "Checking NEORV32.DEVNULL text output. NEORV32.DEVNULL text output is:"
cat neorv32.devnull.out
# Check if reference can be found in output

42
rtl/core/neorv32_devnull.vhd
View file

@ -3,6 +3,7 @@
-- # ********************************************************************************************* #
-- # In simulation: This unit will output the lowest 8 bit of the written data as ASCII chars #
-- # to the simulator console and to a text file ("neorv32.devnull.out"). #
-- # The complete data 32-bit data word is dumped to "neorv32.devnull.data.out". #
-- # In real hardware: This unit implements a "/dev/null" device. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
@ -61,7 +62,8 @@ end neorv32_devnull;
architecture neorv32_devnull_rtl of neorv32_devnull is
-- configuration --
constant sim_output_en_c : boolean := true; -- output lowest byte as char to simulator when enabled
constant sim_text_output_en_c : boolean := true; -- output lowest byte as char to simulator and file when enabled
constant sim_data_output_en_c : boolean := true; -- dump 32-word to file when enabled
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
@ -80,25 +82,35 @@ begin
-- Read/Write Access ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
rw_access: process(clk_i)
file file_devnull_out : text open write_mode is "neorv32.devnull.out";
file file_devnull_text_out : text open write_mode is "neorv32.devnull.out";
file file_devnull_data_out : text open write_mode is "neorv32.devnull.data.out";
variable i : integer;
variable la, lb : line; -- we need to variables here since "writeline" seems to flush the source variable
variable la, lb, lc : line; -- we need several variables here since "writeline" seems to flush the source variable
begin
if rising_edge(clk_i) then
ack_o <= acc_en and (wren_i or rden_i);
if ((acc_en and wren_i and ben_i(0)) = '1') and (sim_output_en_c = true) then
-- print lowest byte as ASCII to console --
i := to_integer(unsigned(data_i(7 downto 0)));
if (i >= 128) then -- out of range?
i := 0;
if (acc_en = '1') and (wren_i = '1') then
if (sim_text_output_en_c = true) and (ben_i(0) = '1') then
-- print lowest byte as ASCII to console --
i := to_integer(unsigned(data_i(7 downto 0)));
if (i >= 128) then -- out of range?
i := 0;
end if;
if (i /= 10) and (i /= 13) then -- skip line breaks - they are issued via "writeline"
write(la, character'val(i));
write(lb, character'val(i));
end if;
if (i = 10) then -- line break: write to screen and file
writeline(output, la);
writeline(file_devnull_text_out, lb);
end if;
end if;
if (i /= 10) and (i /= 13) then -- skip line breaks - they are issued via "writeline"
write(la, character'val(i));
write(lb, character'val(i));
end if;
if (i = 10) then -- line break: write to screen and file
writeline(output, la);
writeline(file_devnull_out, lb);
if (sim_data_output_en_c = true) then
-- dump raw data
for x in 7 downto 0 loop
write(lc, to_hexchar_f(data_i(3+x*4 downto 0+x*4))); -- write in hex form
end loop; -- x
writeline(file_devnull_data_out, lc);
end if;
end if;
end if;

28
rtl/core/neorv32_package.vhd
View file

@ -53,6 +53,7 @@ package neorv32_package is
function and_all_f( a : std_ulogic_vector) return std_ulogic;
function xor_all_f( a : std_ulogic_vector) return std_ulogic;
function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
-- Processor-internal Address Space Layout ------------------------------------------------
-- -------------------------------------------------------------------------------------------
@ -1063,4 +1064,31 @@ package body neorv32_package is
return tmp_v;
end function xnor_all_f;
-- Function: Convert to hex char ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
variable output_v : character;
begin
case (input) is
when x"0" => output_v := '0';
when x"1" => output_v := '1';
when x"2" => output_v := '2';
when x"3" => output_v := '3';
when x"4" => output_v := '4';
when x"5" => output_v := '5';
when x"6" => output_v := '6';
when x"7" => output_v := '7';
when x"8" => output_v := '8';
when x"9" => output_v := '9';
when x"a" => output_v := 'a';
when x"b" => output_v := 'b';
when x"c" => output_v := 'c';
when x"d" => output_v := 'd';
when x"e" => output_v := 'e';
when x"f" => output_v := 'f';
when others => output_v := '?';
end case;
return output_v;
end function to_hexchar_f;
end neorv32_package;

2
sim/ghdl/ghdl_sim.sh
View file

@ -59,6 +59,8 @@ touch neorv32.testbench_uart.out
chmod 777 neorv32.testbench_uart.out
touch neorv32.devnull.out
chmod 777 neorv32.devnull.out
touch neorv32.devnull.data.out
chmod 777 neorv32.devnull.data.out
# Run simulation
ghdl -e --work=neorv32 neorv32_tb