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[rtl/system_integration] add d-cache generics

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stnolting 2023-03-25 14:32:34 +01:00
parent 7dff3a75e8
commit 495639a663
3 changed files with 25 additions and 0 deletions
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10
rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd
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@ -95,6 +95,11 @@ entity neorv32_top_avalonmm is
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- Internal Data Cache (dCACHE) --
DCACHE_EN : boolean := false; -- implement data cache
DCACHE_NUM_BLOCKS : natural := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
@ -277,6 +282,11 @@ begin
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE,
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY,
-- Internal Data Cache (dCACHE) --
DCACHE_EN => DCACHE_EN,
DCACHE_NUM_BLOCKS => DCACHE_NUM_BLOCKS,
DCACHE_BLOCK_SIZE => DCACHE_BLOCK_SIZE,
-- External memory interface (WISHBONE) --
MEM_EXT_EN => true,
MEM_EXT_TIMEOUT => 0,

8
rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
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@ -88,6 +88,10 @@ entity neorv32_SystemTop_axi4lite is
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- Internal Data Cache (dCACHE) --
DCACHE_EN : boolean := false; -- implement data cache
DCACHE_NUM_BLOCKS : natural := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge
@ -340,6 +344,10 @@ begin
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- Internal Data Cache (dCACHE) --
DCACHE_EN => DCACHE_EN, -- implement data cache
DCACHE_NUM_BLOCKS => DCACHE_NUM_BLOCKS, -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE => DCACHE_BLOCK_SIZE, -- d-cache: block size in bytes (min 4), has to be a power of 2
-- External memory interface --
MEM_EXT_EN => true, -- implement external memory bus interface?
MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled)

7
rtl/system_integration/neorv32_litex_core_complex.vhd
View file

@ -154,6 +154,9 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
icache_nb => ( 0, 0, 8, 8 ), -- number of cache blocks (lines), power of two
icache_bs => ( 0, 0, 64, 256 ), -- size of cache clock (lines) in bytes, power of two
icache_as => ( 1, 1, 1, 2 ), -- associativity (1 or 2)
dcache_en => ( false, false, true, true ), -- instruction data enabled
dcache_nb => ( 0, 0, 8, 8 ), -- number of cache blocks (lines), power of two
dcache_bs => ( 0, 0, 64, 256 ), -- size of cache clock (lines) in bytes, power of two
mtime => ( false, true, true, true ) -- RISC-V machine system timers
);
@ -193,6 +196,10 @@ begin
ICACHE_NUM_BLOCKS => configs_c.icache_nb(CONFIG), -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE => configs_c.icache_bs(CONFIG), -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY => configs_c.icache_as(CONFIG), -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- Internal Data Cache (dCACHE) --
DCACHE_EN => configs_c.dcache_en(CONFIG), -- implement data cache
DCACHE_NUM_BLOCKS => configs_c.dcache_nb(CONFIG), -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE => configs_c.dcache_bs(CONFIG), -- d-cache: block size in bytes (min 4), has to be a power of 2
-- External memory interface (WISHBONE) --
MEM_EXT_EN => true, -- implement external memory bus interface?
MEM_EXT_TIMEOUT => wb_timeout_c, -- cycles after a pending bus access auto-terminates (0 = disabled)