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[sw/example/floating_point] update
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2 changed files with 119 additions and 48 deletions
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@ -1,30 +1,24 @@
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# NEORV32 `Zfinx` Floating-Point Extension
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The NEORV32 floating-point unit (FPU) implements the `Zfinx` RISC-V extension. The extensions can be enabled via the `CPU_EXTENSION_RISCV_Zfinx` top configuration generic.
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The NEORV32 floating-point unit (FPU) implements the `Zfinx` RISC-V extension. The extension can be
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enabled via the `CPU_EXTENSION_RISCV_Zfinx` top configuration generic.
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The RISC-V `Zfinx` single-precision floating-point extensions uses the integer register file `x` instead of the dedicated floating-point `f` register file (which is
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defined by the RISC-V `F` single-precision floating-point extension). Hence, the standard data transfer instructions from the `F` extension are **not** available in `Zfinx`:
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The RISC-V `Zfinx` single-precision floating-point extensions uses the integer register file `x` instead
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of a dedicated floating-point `f` register file (which is defined by the RISC-V `F` single-precision
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floating-point extension). Hence, the standard data transfer instructions from the `F` extension are
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**not** available in `Zfinx`:
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* floating-point load/store operations (`FLW`, `FSW`) and their compressed versions
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* integer register file `x` <-> floating point register file `f` move operations (`FMV.W.X`, `FMV.X.W`)
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:information_source: More information regarding the RISC-V `Zfinx` single-precision floating-point extension can be found in the official GitHub repo:
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[`github.com/riscv/riscv-zfinx`](https://github.com/riscv/riscv-zfinx).
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:warning: The RISC-V `Zfinx` extension is not officially ratified yet, but it is assumed to remain unchanged. Hence, it is not supported by the upstream RISC-V GCC port.
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Make sure you **do not** use the `f` ISA attribute when compiling applications that use floating-point arithmetic (`MARCH=rv32i*f*` is **NOT ALLOWED!**).
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### :warning: FPU Limitations
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* The FPU **does not support subnormal numbers** yet. Subnormal FPU inputs and subnormal FPU results are always *flushed to zero*. The *classify* instruction `FCLASS` will never set the "subnormal" mask bits.
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* Rounding mode `ob100` "round to nearest, ties to max magnitude" is not supported yet (this and all invalid rounding mode configurations behave as "round towards zero" (truncation)).
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:information_source: See the according section of the NEORV32 data sheet for more information.
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## Intrinsic Library
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The NEORV32 `Zfinx` floating-point extension can still be used using the provided **intrinsic library**. This library uses "custom" inline assmbly instructions
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wrapped within normal C-language functions. Each original instruction of the extension can be utilized using an according intrinsic function.
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The NEORV32 `Zfinx` floating-point extension can still be used using the provided **intrinsic library**. This
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library uses "custom" inline assembly instructions wrapped within normal C-language functions. Each original
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instruction of the extension can be utilized using an according intrinsic function.
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For example, the floating-point addition instruction `FADD.S` can be invoked using the according intrinsic function:
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@ -32,21 +26,98 @@ For example, the floating-point addition instruction `FADD.S` can be invoked usi
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float riscv_intrinsic_fadds(float rs1, float rs2)
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```
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The pure-software emulation instruction, which uses the standard built-in functions to execute all floating-point operations, is available via wrapper function. The
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emulation function for the `FADD.S` instruction is:
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The pure-software emulation instruction, which uses the standard built-in functions to execute all
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floating-point operations, is available via wrapper function. The emulation function for the `FADD.S` instruction is:
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```c
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float riscv_emulate_fadds(float rs1, float rs2)
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```
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The emulation functions as well as the available intrinsics for the `Zfinx` extension are located in `neorv32_zfinx_extension_intrinsics.h`.
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The provided test program `main.c` verifies all currently implemented `Zfinx` instructions by checking the functionality against the pure software-based emulation model
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(GCC soft-float library).
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The emulation functions as well as the available intrinsics for the `Zfinx` extension are located in
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`neorv32_zfinx_extension_intrinsics.h`. The provided test program `main.c` verifies all currently implemented
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`Zfinx` instructions by checking the functionality against the pure software-based emulation model (GCC soft-float library).
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## Resources
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## Exemplary Test Output
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* Great page with online calculators for floating-point arithmetic: [http://www.ecs.umass.edu/ece/koren/arith/simulator/](http://www.ecs.umass.edu/ece/koren/arith/simulator/)
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* A handy tool for visualizing floating-point numbers in their binary representation: [https://www.h-schmidt.net/FloatConverter/IEEE754.html](https://www.h-schmidt.net/FloatConverter/IEEE754.html)
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* This helped me to understand what results the different FPU operation generate when having "special" inputs like NaN: [https://techdocs.altium.com/display/FPGA/IEEE+754+Standard+-+Overview](https://techdocs.altium.com/display/FPGA/IEEE+754+Standard+-+Overview)
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```
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<<< Zfinx extension test >>>
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SILENT_MODE enabled (only showing actual errors)
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Test cases per instruction: 1000000
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NOTE: The NEORV32 FPU does not support subnormal numbers yet. Subnormal numbers are flushed to zero.
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#0: FCVT.S.WU (unsigned integer to float)...
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Errors: 0/1000000 [ok]
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#1: FCVT.S.W (signed integer to float)...
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Errors: 0/1000000 [ok]
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#2: FCVT.WU.S (float to unsigned integer)...
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Errors: 0/1000000 [ok]
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#3: FCVT.W.S (float to signed integer)...
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Errors: 0/1000000 [ok]
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#4: FADD.S (addition)...
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Errors: 0/1000000 [ok]
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#5: FSUB.S (subtraction)...
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Errors: 0/1000000 [ok]
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#6: FMUL.S (multiplication)...
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Errors: 0/1000000 [ok]
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#7: FMIN.S (select minimum)...
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Errors: 0/1000000 [ok]
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#8: FMAX.S (select maximum)...
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Errors: 0/1000000 [ok]
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#9: FEQ.S (compare if equal)...
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Errors: 0/1000000 [ok]
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#10: FLT.S (compare if less-than)...
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Errors: 0/1000000 [ok]
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#11: FLE.S (compare if less-than-or-equal)...
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Errors: 0/1000000 [ok]
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#12: FSGNJ.S (sign-injection)...
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Errors: 0/1000000 [ok]
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#13: FSGNJN.S (sign-injection NOT)...
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Errors: 0/1000000 [ok]
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#14: FSGNJX.S (sign-injection XOR)...
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Errors: 0/1000000 [ok]
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#15: FCLASS.S (classify)...
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Errors: 0/1000000 [ok]
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# unsupported FDIV.S (division) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x000006A8, INST=0x18A484D3 </RTE>
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[ok]
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# unsupported FSQRT.S (square root) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x000006E0, INST=0x580484D3 </RTE>
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[ok]
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# unsupported FMADD.S (fused multiply-add) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x0000071E, INST=0x1EA484C3 </RTE>
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[ok]
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# unsupported FMSUB.S (fused multiply-sub) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x0000075C, INST=0x1EA484C7 </RTE>
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[ok]
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# unsupported FNMSUB.S (fused negated multiply-sub) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x0000079A, INST=0x1EA484CF </RTE>
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[ok]
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# unsupported FNMADD.S (fused negated multiply-add) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x000007D8, INST=0x1EA484CF </RTE>
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[ok]
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[Zfinx extension verification successful!]
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```
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@ -178,7 +178,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fadds(float rs1, fl
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0000000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0000000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -196,7 +196,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fsubs(float rs1, fl
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0000100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0000100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -214,7 +214,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fmuls(float rs1, fl
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0001000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0001000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -232,7 +232,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fmins(float rs1, fl
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0010100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -250,7 +250,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fmaxs(float rs1, fl
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010100, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0010100, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
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return res.float_value;
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}
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@ -266,7 +266,7 @@ inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_wus(float r
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float_conv_t opa;
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opa.float_value = rs1;
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return CUSTOM_INSTR_R1_TYPE(0b1100000, 0b00001, opa.binary_value, 0b000, 0b1010011);
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return CUSTOM_INSTR_R2_TYPE(0b1100000, 0b00001, opa.binary_value, 0b000, 0b1010011);
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}
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@ -281,7 +281,7 @@ inline int32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_ws(float rs1
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float_conv_t opa;
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opa.float_value = rs1;
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return (int32_t)CUSTOM_INSTR_R1_TYPE(0b1100000, 0b00000, opa.binary_value, 0b000, 0b1010011);
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return (int32_t)CUSTOM_INSTR_R2_TYPE(0b1100000, 0b00000, opa.binary_value, 0b000, 0b1010011);
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}
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@ -295,7 +295,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fcvt_swu(uint32_t r
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float_conv_t res;
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res.binary_value = CUSTOM_INSTR_R1_TYPE(0b1101000, 0b00001, rs1, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b1101000, 0b00001, rs1, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -310,7 +310,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fcvt_sw(int32_t rs1
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float_conv_t res;
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res.binary_value = CUSTOM_INSTR_R1_TYPE(0b1101000, 0b00000, rs1, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b1101000, 0b00000, rs1, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -328,7 +328,7 @@ inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_feqs(float rs1,
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opa.float_value = rs1;
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opb.float_value = rs2;
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return CUSTOM_INSTR_R2_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b010, 0b1010011);
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return CUSTOM_INSTR_R3_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b010, 0b1010011);
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}
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@ -345,7 +345,7 @@ inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_flts(float rs1,
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opa.float_value = rs1;
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opb.float_value = rs2;
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return CUSTOM_INSTR_R2_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
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return CUSTOM_INSTR_R3_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
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}
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@ -362,7 +362,7 @@ inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fles(float rs1,
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opa.float_value = rs1;
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opb.float_value = rs2;
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return CUSTOM_INSTR_R2_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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return CUSTOM_INSTR_R3_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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}
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@ -379,7 +379,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjs(float rs1, f
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -397,7 +397,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjns(float rs1,
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
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return res.float_value;
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}
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@ -415,7 +415,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjxs(float rs1,
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b010, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b010, 0b1010011);
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return res.float_value;
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}
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@ -431,7 +431,7 @@ inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fclasss(float rs
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float_conv_t opa;
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opa.float_value = rs1;
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return CUSTOM_INSTR_R1_TYPE(0b1110000, 0b00000, opa.binary_value, 0b001, 0b1010011);
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return CUSTOM_INSTR_R2_TYPE(0b1110000, 0b00000, opa.binary_value, 0b001, 0b1010011);
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}
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@ -454,7 +454,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fdivs(float rs1, fl
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opa.float_value = rs1;
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opb.float_value = rs2;
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0001100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R3_TYPE(0b0001100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -472,7 +472,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fsqrts(float rs1) {
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float_conv_t opa, res;
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opa.float_value = rs1;
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res.binary_value = CUSTOM_INSTR_R1_TYPE(0b0101100, 0b00000, opa.binary_value, 0b000, 0b1010011);
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res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0101100, 0b00000, opa.binary_value, 0b000, 0b1010011);
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return res.float_value;
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}
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@ -494,7 +494,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fmadds(float rs1, f
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opb.float_value = rs2;
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opc.float_value = rs3;
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res.binary_value = CUSTOM_INSTR_R3_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1000011);
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res.binary_value = CUSTOM_INSTR_R4_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1000011);
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return res.float_value;
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}
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@ -516,7 +516,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fmsubs(float rs1, f
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opb.float_value = rs2;
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opc.float_value = rs3;
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res.binary_value = CUSTOM_INSTR_R3_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1000111);
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res.binary_value = CUSTOM_INSTR_R4_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1000111);
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return res.float_value;
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}
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@ -538,7 +538,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fnmsubs(float rs1,
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opb.float_value = rs2;
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opc.float_value = rs3;
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res.binary_value = CUSTOM_INSTR_R3_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1001011);
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res.binary_value = CUSTOM_INSTR_R4_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1001011);
|
||||
return res.float_value;
|
||||
}
|
||||
|
||||
|
|
@ -560,7 +560,7 @@ inline float __attribute__ ((always_inline)) riscv_intrinsic_fnmadds(float rs1,
|
|||
opb.float_value = rs2;
|
||||
opc.float_value = rs3;
|
||||
|
||||
res.binary_value = CUSTOM_INSTR_R3_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1001111);
|
||||
res.binary_value = CUSTOM_INSTR_R4_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1001111);
|
||||
return res.float_value;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue