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[rtl/system_integration] generic cleanups
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3 changed files with 20 additions and 9 deletions
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@ -46,7 +46,8 @@ entity neorv32_top_avalonmm is
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generic (
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-- General --
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CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
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VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
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CUSTOM_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID
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INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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@ -228,9 +229,9 @@ begin
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generic map (
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-- General --
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CLOCK_FREQUENCY => CLOCK_FREQUENCY,
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HW_THREAD_ID => HW_THREAD_ID,
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HART_ID => HART_ID,
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VENDOR_ID => VENDOR_ID,
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CUSTOM_ID => CUSTOM_ID,
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INT_BOOTLOADER_EN => INT_BOOTLOADER_EN,
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN,
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@ -49,8 +49,9 @@ entity neorv32_SystemTop_axi4lite is
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-- ------------------------------------------------------------
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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CUSTOM_ID : std_logic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
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VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
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CUSTOM_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID
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INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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@ -299,8 +300,9 @@ begin
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generic map (
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-- General --
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CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
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HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (hartid)
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CUSTOM_ID => CUSTOM_ID_INT, -- custom user-defined ID
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HART_ID => HART_ID, -- hardware thread ID
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VENDOR_ID => VENDOR_ID, -- vendor's JEDEC ID
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CUSTOM_ID => CUSTOM_ID, -- custom user-defined ID
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INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement on-chip debugger
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@ -37,7 +37,7 @@
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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@ -108,7 +108,12 @@ end neorv32_litex_core_complex;
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architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
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-- advance configuration --
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-- identifiers --
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constant hart_id_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID ("core ID")
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constant jedec_id_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC manufacturer ID
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constant user_id_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user ID
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-- advanced configuration --
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constant num_configs_c : natural := 4; -- number of pre-defined configurations
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constant wb_timeout_c : natural := 4096; -- external bus interface timeout cycles
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constant big_endian_c : boolean := false; -- external bus interface endianness; default is little-endian
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@ -160,6 +165,9 @@ begin
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generic map (
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-- General --
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CLOCK_FREQUENCY => 0, -- clock frequency of clk_i in Hz [not required by the core complex]
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HART_ID => hart_id_c, -- hardware thread ID
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VENDOR_ID => jedec_id_c, -- vendor's JEDEC ID
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CUSTOM_ID => user_id_c, -- custom user-defined ID
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN => DEBUG, -- implement on-chip debugger
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-- RISC-V CPU Extensions --
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