[rtl/system_integration] generic cleanups

This commit is contained in:
stnolting 2023-03-18 16:04:21 +01:00
parent c89f5f08dc
commit 4c65442074
3 changed files with 20 additions and 9 deletions

View file

@ -46,7 +46,8 @@ entity neorv32_top_avalonmm is
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
CUSTOM_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
@ -228,9 +229,9 @@ begin
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
HW_THREAD_ID => HW_THREAD_ID,
HART_ID => HART_ID,
VENDOR_ID => VENDOR_ID,
CUSTOM_ID => CUSTOM_ID,
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN,
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN,

View file

@ -49,8 +49,9 @@ entity neorv32_SystemTop_axi4lite is
-- ------------------------------------------------------------
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
CUSTOM_ID : std_logic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
CUSTOM_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID
INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
@ -299,8 +300,9 @@ begin
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (hartid)
CUSTOM_ID => CUSTOM_ID_INT, -- custom user-defined ID
HART_ID => HART_ID, -- hardware thread ID
VENDOR_ID => VENDOR_ID, -- vendor's JEDEC ID
CUSTOM_ID => CUSTOM_ID, -- custom user-defined ID
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement on-chip debugger

View file

@ -37,7 +37,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
@ -108,7 +108,12 @@ end neorv32_litex_core_complex;
architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
-- advance configuration --
-- identifiers --
constant hart_id_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID ("core ID")
constant jedec_id_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC manufacturer ID
constant user_id_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user ID
-- advanced configuration --
constant num_configs_c : natural := 4; -- number of pre-defined configurations
constant wb_timeout_c : natural := 4096; -- external bus interface timeout cycles
constant big_endian_c : boolean := false; -- external bus interface endianness; default is little-endian
@ -160,6 +165,9 @@ begin
generic map (
-- General --
CLOCK_FREQUENCY => 0, -- clock frequency of clk_i in Hz [not required by the core complex]
HART_ID => hart_id_c, -- hardware thread ID
VENDOR_ID => jedec_id_c, -- vendor's JEDEC ID
CUSTOM_ID => user_id_c, -- custom user-defined ID
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN => DEBUG, -- implement on-chip debugger
-- RISC-V CPU Extensions --