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🚀 preparing release v1.10.0

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stnolting 2024-06-16 20:46:25 +02:00
parent 2cf9144c23
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4 changed files with 4 additions and 3 deletions
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1
CHANGELOG.md
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 16.05.2024 | [**:rocket:1.10.0**](https://github.com/stnolting/neorv32/releases/tag/v1.10.0) | **New release** | |
| 15.06.2024 | 1.9.9.9 | :sparkles: add pre-configured example project for Eclipse IDE | [#926](https://github.com/stnolting/neorv32/pull/926) |
| 14.06.2024 | 1.9.9.8 | minor rtl edits/cleanups; increase bootloader's auto-boot timeout from 8s to 10s | [#925](https://github.com/stnolting/neorv32/pull/925) |
| 07.06.2024 | 1.9.9.7 | :sparkles: re-add TRNG "data available" interrupt | [#922](https://github.com/stnolting/neorv32/pull/922) |

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docs/attrs.adoc
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@ -1,6 +1,6 @@
:keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic, safety
:description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
:revnumber: v1.9.9
:revnumber: v1.10.0
:doctype: book
:sectnums:
:stem:

2
rtl/core/neorv32_package.vhd
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@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090909"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100000"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

2
sw/svd/neorv32.svd
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@ -4,7 +4,7 @@
<vendor>stnolting</vendor>
<name>neorv32</name>
<series>RISC-V</series>
<version>1.9.9</version>
<version>1.10.0</version>
<description>The NEORV32 RISC-V Processor</description>
<!-- CPU core -->