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https://github.com/stnolting/neorv32.git
synced 2025-04-23 21:57:33 -04:00
[sw/cpu_test] improved PMP tests
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stnolting
parent
ea03d97148
commit
4f6c90dcb4
1 changed files with 144 additions and 73 deletions
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@ -49,8 +49,6 @@
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/**@{*/
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/** UART BAUD rate */
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#define BAUD_RATE 19200
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//** Set 1 to run external memory test */
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#define EXT_MEM_TEST 1
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//** Reachable unaligned address */
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#define ADDR_UNALIGNED 0x00000002
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//** Unreachable aligned address */
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@ -97,8 +95,8 @@ int cnt_test = 0;
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**************************************************************************/
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int main() {
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register uint32_t tmp_a;
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uint32_t i;
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register uint32_t tmp_a, tmp_b, tmp_c;
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uint32_t i, j;
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volatile uint32_t dummy_dst __attribute__((unused));
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union {
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@ -293,7 +291,7 @@ int main() {
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// check for access exception
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if (exception_handler_answer == 0xFFFFFFFF) { // no exception -> access ok -> CSR exists
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neorv32_uart_printf(" + 0x%x\n", csr_addr_cnt);
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neorv32_uart_printf(" + 0x%x\n", csr_addr_cnt);
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i++;
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}
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}
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@ -393,41 +391,43 @@ int main() {
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// External memory interface test
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// ----------------------------------------------------------
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exception_handler_answer = 0xFFFFFFFF;
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neorv32_uart_printf("[%i] External memory access test: ", cnt_test);
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#if (EXT_MEM_TEST == 1)
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cnt_test++;
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neorv32_uart_printf("[%i] External memory access (@ 0x%x) test: ", cnt_test, (uint32_t)EXT_MEM_BASE);
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// create test program in RAM
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static const uint32_t dummy_ext_program[2] __attribute__((aligned(8))) = {
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0x3407D073, // csrwi mscratch, 15
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0x00008067 // ret (32-bit)
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};
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if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT)) {
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cnt_test++;
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// copy to external memory
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if (memcpy((void*)EXT_MEM_BASE, (void*)&dummy_ext_program, (size_t)sizeof(dummy_ext_program)) == NULL) {
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test_fail();
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}
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else {
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// create test program in RAM
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static const uint32_t dummy_ext_program[2] __attribute__((aligned(8))) = {
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0x3407D073, // csrwi mscratch, 15
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0x00008067 // ret (32-bit)
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};
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// execute program
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tmp_a = (uint32_t)EXT_MEM_BASE; // call the dummy sub program
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asm volatile ("jalr ra, %[input_i]" : : [input_i] "r" (tmp_a));
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if (exception_handler_answer == 0xFFFFFFFF) { // make sure there was no exception
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if (neorv32_cpu_csr_read(CSR_MSCRATCH) == 15) { // make sure the program was executed in the right way
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test_ok();
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// copy to external memory
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if (memcpy((void*)EXT_MEM_BASE, (void*)&dummy_ext_program, (size_t)sizeof(dummy_ext_program)) == NULL) {
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test_fail();
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}
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else {
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// execute program
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tmp_a = (uint32_t)EXT_MEM_BASE; // call the dummy sub program
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asm volatile ("jalr ra, %[input_i]" : : [input_i] "r" (tmp_a));
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if (exception_handler_answer == 0xFFFFFFFF) { // make sure there was no exception
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if (neorv32_cpu_csr_read(CSR_MSCRATCH) == 15) { // make sure the program was executed in the right way
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test_ok();
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}
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else {
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test_fail();
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}
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}
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else {
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test_fail();
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}
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}
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else {
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test_fail();
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}
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}
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#else
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neorv32_uart_printf("skipped (disabled)\n");
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#endif
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else {
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neorv32_uart_printf("skipped (external memory interface not implemented)\n");
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}
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// ----------------------------------------------------------
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@ -834,46 +834,50 @@ int main() {
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exception_handler_answer = 0xFFFFFFFF;
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neorv32_uart_printf("[%i] FIRQ1 (fast IRQ1) interrupt test (via GPIO): ", cnt_test);
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if (neorv32_gpio_available()) {
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cnt_test++;
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if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
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if (neorv32_gpio_available()) {
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cnt_test++;
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// clear output port
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neorv32_gpio_port_set(0);
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// clear output port
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neorv32_gpio_port_set(0);
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// configure GPIO.in(31) for pin-change IRQ
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neorv32_gpio_pin_change_config(0x80000000);
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// configure GPIO.in(31) for pin-change IRQ
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neorv32_gpio_pin_change_config(0x80000000);
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// trigger pin-change IRQ by setting GPIO.out(31)
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// the testbench connects GPIO.out => GPIO.in
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neorv32_gpio_pin_set(31);
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// trigger pin-change IRQ by setting GPIO.out(31)
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// the testbench connects GPIO.out => GPIO.in
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neorv32_gpio_pin_set(31);
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// wait some time for the IRQ to arrive the CPU
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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// wait some time for the IRQ to arrive the CPU
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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if (exception_handler_answer == TRAP_CODE_FIRQ_1) {
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test_ok();
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if (exception_handler_answer == TRAP_CODE_FIRQ_1) {
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test_ok();
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}
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else {
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test_fail();
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}
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// disable GPIO pin-change IRQ
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neorv32_gpio_pin_change_config(0);
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// clear output port
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neorv32_gpio_port_set(0);
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}
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else {
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test_fail();
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neorv32_uart_printf("skipped (GPIO not implemented)\n");
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}
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// disable GPIO pin-change IRQ
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neorv32_gpio_pin_change_config(0);
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// clear output port
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neorv32_gpio_port_set(0);
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}
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else {
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neorv32_uart_printf("skipped (GPIO not implemented)\n");
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neorv32_uart_printf("skipped (on real hardware)\n");
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}
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// ----------------------------------------------------------
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// Fast interrupt channel 2 (UART)
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// ----------------------------------------------------------
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@ -1097,7 +1101,6 @@ int main() {
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// ----------------------------------------------------------
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// Test physical memory protection
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// ----------------------------------------------------------
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exception_handler_answer = 0xFFFFFFFF;
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neorv32_uart_printf("[%i] Physical memory protection (PMP): ", cnt_test);
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// check if PMP is implemented
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@ -1105,13 +1108,37 @@ int main() {
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// Test access to protected region
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// ---------------------------------------------
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neorv32_uart_printf("Creating protected page (NAPOT, 64kB) @ 0xFFFFA000, [!x, !w, r]... ");
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exception_handler_answer = 0xFFFFFFFF;
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cnt_test++;
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neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffdfff); // 64k area @ 0xFFFFA000
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // NAPOT, read permission, NO write and NO execute permissions
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// check min granulartiy
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0);
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neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
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tmp_a = neorv32_cpu_csr_read(0x3b0);
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if ((neorv32_cpu_csr_read(CSR_PMPADDR0) == 0xffffdfff) && (neorv32_cpu_csr_read(CSR_PMPCFG0) == 0b00011001)) {
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// find least-significat set bit
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for (i=31; i!=0; i--) {
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if (((tmp_a >> i) & 1) == 0) {
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break;
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}
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}
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tmp_a = SYSINFO_DSPACE_BASE; // base address of protected region
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tmp_b = 0;
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for (j=i; j!=0; j--) {
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tmp_b = tmp_b << 1;
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tmp_b = tmp_b | 1;
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}
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tmp_c = tmp_a & (~tmp_b); // clear LSBs in base address
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tmp_c = tmp_c | tmp_b; // set region size config
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neorv32_uart_printf("Creating protected page (NAPOT, [!X,!W,R], %u bytes) @ 0x%x (PMPADDR = 0x%x): ", (uint32_t)(1 << (i+1+2)), tmp_a, tmp_c);
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neorv32_cpu_csr_write(CSR_PMPADDR0, tmp_c); // 64k area @ 0xFFFFA000
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // NAPOT, read permission, NO write and NO execute permissions
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if ((neorv32_cpu_csr_read(CSR_PMPADDR0) == tmp_c) && (neorv32_cpu_csr_read(CSR_PMPCFG0) == 0b00011001) && (exception_handler_answer == 0xFFFFFFFF)) {
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test_ok();
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}
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else {
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@ -1119,15 +1146,40 @@ int main() {
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}
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// ------ LOAD: should work ------
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neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] load test: ", cnt_test);
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// ------ EXECUTE: should fail ------
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neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] eeecute test: ", cnt_test);
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cnt_test++;
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exception_handler_answer = 0xFFFFFFFF;
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// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
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neorv32_cpu_goto_user_mode();
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{
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asm volatile ("lw zero, 0xFFFFFF90(zero)"); // MTIME load access, should work
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asm volatile ("jalr ra, %[input_i]" : : [input_i] "r" (tmp_a)); // call address to execute -> should fail
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}
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if (exception_handler_answer == 0xFFFFFFFF) {
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// switch back to machine mode (if not allready)
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asm volatile ("ecall");
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test_fail();
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}
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else {
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// switch back to machine mode (if not allready)
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asm volatile ("ecall");
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test_ok();
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}
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// ------ LOAD: should work ------
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neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] read test: ", cnt_test);
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cnt_test++;
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exception_handler_answer = 0xFFFFFFFF;
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// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
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neorv32_cpu_goto_user_mode();
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{
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asm volatile ("lw zero, 0(%[input_i])" : : [input_i] "r" (tmp_a)); // load access -> should work
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}
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if (exception_handler_answer == 0xFFFFFFFF) {
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@ -1145,14 +1197,14 @@ int main() {
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// ------ STORE: should fail ------
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neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] store test: ", cnt_test);
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neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] write test: ", cnt_test);
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cnt_test++;
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exception_handler_answer = 0xFFFFFFFF;
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// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
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neorv32_cpu_goto_user_mode();
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{
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asm volatile ("sw zero, 0xFFFFFF90(zero)"); // MTIME store access, should fail
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asm volatile ("sw zero, 0(%[input_i])" : : [input_i] "r" (tmp_a)); // store access -> should fail
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}
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if (exception_handler_answer == TRAP_CODE_S_ACCESS) {
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@ -1169,12 +1221,12 @@ int main() {
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}
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// ------ Lock test ------
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neorv32_uart_printf("[%i] PMP: Locking pmpcfg0 [mode=off]: ", cnt_test);
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// ------ Lock test - pmpcfg0.0 ------
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neorv32_uart_printf("[%i] - PMP: pmpcfg0.0 [mode=off] lock test: ", cnt_test);
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cnt_test++;
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exception_handler_answer = 0xFFFFFFFF;
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0b10000001); // locked but entry is deactivated (mode = off)
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0b10000001); // locked, but entry is deactivated (mode = off)
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// make sure a locked cfg cannot be written
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tmp_a = neorv32_cpu_csr_read(CSR_PMPCFG0);
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@ -1187,6 +1239,25 @@ int main() {
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test_ok();
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}
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// ------ Lock test - pmpaddr0 ------
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neorv32_uart_printf("[%i] - PMP: pmpaddr0 [mode=off] lock test: ", cnt_test);
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cnt_test++;
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exception_handler_answer = 0xFFFFFFFF;
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0b10000001); // locked, but entry is deactivated (mode = off)
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// make sure a locked cfg cannot be written
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tmp_a = neorv32_cpu_csr_read(CSR_PMPADDR0);
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neorv32_cpu_csr_write(CSR_PMPADDR0, 0xABABCDCD); // try to re-write ADDR content
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if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPADDR0)) || (exception_handler_answer != 0xFFFFFFFF)) {
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test_fail();
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}
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else {
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test_ok();
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}
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}
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else {
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neorv32_uart_printf("not implemented\n");
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@ -1196,8 +1267,8 @@ int main() {
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// ----------------------------------------------------------
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// Final test reports
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// ----------------------------------------------------------
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neorv32_uart_printf("\n\nExecuted instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET));
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neorv32_uart_printf( "Required clock cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE));
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neorv32_uart_printf("\nExecuted instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET));
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neorv32_uart_printf( "Required clock cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE));
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neorv32_uart_printf("\nTest results:\nOK: %i/%i\nFAILED: %i/%i\n\n", cnt_ok, cnt_test, cnt_fail, cnt_test);
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