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[sw] update GPTMR HAL
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stnolting
parent
d31320a501
commit
500f3b647e
3 changed files with 158 additions and 28 deletions
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@ -3,7 +3,7 @@
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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@ -49,22 +49,29 @@
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/**@{*/
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/** GPTMR module prototype */
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typedef volatile struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_GPTMR_CTRL_enum) */
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uint32_t THRES; /**< offset 4: threshold register */
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uint32_t COUNT; /**< offset 8: counter register */
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const uint32_t reserved; /**< offset 12: reserved */
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_GPTMR_CTRL_enum) */
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uint32_t THRES; /**< offset 4: threshold register */
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uint32_t COUNT; /**< offset 8: counter register */
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uint32_t CAPTURE; /**< offset 12: capture register */
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} neorv32_gptmr_t;
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/** GPTMR module hardware access (#neorv32_gptmr_t) */
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#define NEORV32_GPTMR ((neorv32_gptmr_t*) (NEORV32_GPTMR_BASE))
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/** GPTMR control/data register bits */
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/** GPTMR control register bits */
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enum NEORV32_GPTMR_CTRL_enum {
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GPTMR_CTRL_EN = 0, /**< GPTIMR control register(0) (r/w): Timer unit enable */
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GPTMR_CTRL_PRSC0 = 1, /**< GPTIMR control register(1) (r/w): Clock prescaler select bit 0 */
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GPTMR_CTRL_PRSC1 = 2, /**< GPTIMR control register(2) (r/w): Clock prescaler select bit 1 */
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GPTMR_CTRL_PRSC2 = 3, /**< GPTIMR control register(3) (r/w): Clock prescaler select bit 2 */
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GPTMR_CTRL_MODE = 4 /**< GPTIMR control register(4) (r/w): Timer mode: 0=single-shot mode, 1=continuous mode */
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GPTMR_CTRL_EN = 0, /**< GPTMR control register(0) (r/w): GPTMR enable */
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GPTMR_CTRL_PRSC0 = 1, /**< GPTMR control register(1) (r/w): Clock prescaler select bit 0 */
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GPTMR_CTRL_PRSC1 = 2, /**< GPTMR control register(2) (r/w): Clock prescaler select bit 1 */
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GPTMR_CTRL_PRSC2 = 3, /**< GPTMR control register(3) (r/w): Clock prescaler select bit 2 */
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GPTMR_CTRL_IRQM = 4, /**< GPTMR control register(4) (r/w): Enable interrupt on timer match */
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GPTMR_CTRL_IRQC = 5, /**< GPTMR control register(5) (r/w): Enable interrupt on capture trigger */
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GPTMR_CTRL_RISE = 6, /**< GPTMR control register(6) (r/w): Capture on rising edge; capture-mode only */
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GPTMR_CTRL_FALL = 7, /**< GPTMR control register(7) (r/w): Capture on falling edge; capture-mode only */
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GPTMR_CTRL_FILTER = 8, /**< GPTMR control register(8) (r/w): Filter capture input; capture-mode only */
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GPTMR_CTRL_TRIGM = 30, /**< GPTMR control register(30) (r/c): Timer-match has fired, cleared by writing 0 */
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GPTMR_CTRL_TRIGC = 31, /**< GPTMR control register(31) (r/c): Capture-trigger has fired, cleared by writing 0 */
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};
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/**@}*/
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@ -73,11 +80,16 @@ enum NEORV32_GPTMR_CTRL_enum {
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* @name Prototypes
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**************************************************************************/
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/**@{*/
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int neorv32_gptmr_available(void);
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void neorv32_gptmr_setup(int prsc, int mode, uint32_t threshold);
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void neorv32_gptmr_disable(void);
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void neorv32_gptmr_enable(void);
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void neorv32_gptmr_restart(void);
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int neorv32_gptmr_available(void);
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void neorv32_gptmr_setup(int prsc, uint32_t threshold, int match_irq);
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void neorv32_gptmr_capture(int rising, int falling, int filter, int capture_irq);
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void neorv32_gptmr_disable(void);
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void neorv32_gptmr_enable(void);
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int neorv32_gptmr_trigger_matched(void);
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int neorv32_gptmr_trigger_captured(void);
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void neorv32_gptmr_restart(void);
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uint32_t neorv32_gptmr_counter_get(void);
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uint32_t neorv32_gptmr_capture_get(void);
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/**@}*/
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@ -3,7 +3,7 @@
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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@ -61,22 +61,42 @@ int neorv32_gptmr_available(void) {
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/**********************************************************************//**
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* Enable and configure general purpose timer.
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* Reset, enable and configure general purpose timer.
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*
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* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
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* @param[in] mode 0=single-shot mode, 1=continuous mode
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* @param[in] threshold Threshold value to trigger interrupt.
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* @param[in] threshold Threshold value, counter will reset to zero when reaching this.
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* @param[in] match_irq Fire interrupt when counter matches threshold value.
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**************************************************************************/
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void neorv32_gptmr_setup(int prsc, int mode, uint32_t threshold) {
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void neorv32_gptmr_setup(int prsc, uint32_t threshold, int match_irq) {
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NEORV32_GPTMR->CTRL = 0; // reset
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NEORV32_GPTMR->CTRL = 0; // reset configuration
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NEORV32_GPTMR->THRES = threshold;
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NEORV32_GPTMR->COUNT = 0; // reset counter
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uint32_t tmp = 0;
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tmp |= (uint32_t)(1 & 0x01) << GPTMR_CTRL_EN;
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tmp |= (uint32_t)(prsc & 0x07) << GPTMR_CTRL_PRSC0;
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tmp |= (uint32_t)(mode & 0x01) << GPTMR_CTRL_MODE;
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tmp |= (uint32_t)(1 & 0x01) << GPTMR_CTRL_EN;
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tmp |= (uint32_t)(prsc & 0x07) << GPTMR_CTRL_PRSC0;
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tmp |= (uint32_t)(match_irq & 0x01) << GPTMR_CTRL_IRQM;
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NEORV32_GPTMR->CTRL = tmp;
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}
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/**********************************************************************//**
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* Configure timer capture feature.
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* @note This function needs to be called after the general GPTMR setup #neorv32_gptmr_setup.
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*
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* @param[in] rising Capture on rising edge.
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* @param[in] falling Capture on falling edge.
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* @param[in] filter Enable filtering of capture input.
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* @param[in] capture_irq Fire interrupt when on capture trigger.
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**************************************************************************/
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void neorv32_gptmr_capture(int rising, int falling, int filter, int capture_irq) {
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uint32_t tmp = NEORV32_GPTMR->CTRL;
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tmp |= (uint32_t)(rising & 0x01) << GPTMR_CTRL_RISE;
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tmp |= (uint32_t)(falling & 0x01) << GPTMR_CTRL_FALL;
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tmp |= (uint32_t)(filter & 0x01) << GPTMR_CTRL_FILTER;
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tmp |= (uint32_t)(capture_irq & 0x01) << GPTMR_CTRL_IRQC;
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NEORV32_GPTMR->CTRL = tmp;
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}
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@ -100,9 +120,71 @@ void neorv32_gptmr_enable(void) {
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/**********************************************************************//**
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* Reset general purpose timer's counter register.
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* Check if timer match has triggered. Clear trigger flag in that case.
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*
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* @return 1 if match trigger has fired, 0 if not.
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**************************************************************************/
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int neorv32_gptmr_trigger_matched(void) {
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uint32_t tmp = NEORV32_GPTMR->CTRL;
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if (tmp & (1 << GPTMR_CTRL_TRIGM)) {
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tmp &= ~((uint32_t)(1 << GPTMR_CTRL_TRIGM));
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NEORV32_GPTMR->CTRL = tmp;
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return 1;
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}
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else {
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return 0;
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}
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}
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/**********************************************************************//**
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* Check if capture input has triggered. Clear trigger flag in that case.
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*
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* @return 1 if capture trigger has fired, 0 if not.
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**************************************************************************/
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int neorv32_gptmr_trigger_captured(void) {
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uint32_t tmp = NEORV32_GPTMR->CTRL;
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if (tmp & (1 << GPTMR_CTRL_TRIGC)) {
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tmp &= ~((uint32_t)(1 << GPTMR_CTRL_TRIGC));
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NEORV32_GPTMR->CTRL = tmp;
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return 1;
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}
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else {
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return 0;
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}
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}
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/**********************************************************************//**
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* Reset general purpose timer's counter register (timer-mode only).
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**************************************************************************/
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void neorv32_gptmr_restart(void) {
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NEORV32_GPTMR->COUNT = 0;
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}
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/**********************************************************************//**
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* Get current counter value.
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*
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* @return Current counter value.
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**************************************************************************/
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uint32_t neorv32_gptmr_counter_get(void) {
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return NEORV32_GPTMR->COUNT;
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}
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/**********************************************************************//**
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* Get latest capture value.
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*
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* @return Capture timer value.
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**************************************************************************/
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uint32_t neorv32_gptmr_capture_get(void) {
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return NEORV32_GPTMR->CAPTURE;
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}
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@ -674,9 +674,39 @@
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<description>Clock prescaler select</description>
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</field>
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<field>
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<name>GPTMR_CTRL_MODE</name>
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<name>GPTMR_CTRL_IRQM</name>
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<bitRange>[4:4]</bitRange>
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<description>Timer mode: 0=single-shot mode, 1=continuous mode</description>
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<description>Enable interrupt on timer match</description>
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</field>
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<field>
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<name>GPTMR_CTRL_IRQC</name>
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<bitRange>[5:5]</bitRange>
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<description>Enable interrupt on capture trigger</description>
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</field>
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<field>
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<name>GPTMR_CTRL_RISE</name>
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<bitRange>[6:6]</bitRange>
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<description>Capture on rising edge; capture-mode only</description>
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</field>
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<field>
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<name>GPTMR_CTRL_FALL</name>
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<bitRange>[7:7]</bitRange>
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<description>Capture on falling edge; capture-mode only</description>
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</field>
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<field>
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<name>GPTMR_CTRL_FILTER</name>
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<bitRange>[8:8]</bitRange>
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<description>Filter capture input; capture-mode only</description>
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</field>
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<field>
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<name>GPTMR_CTRL_TRIGM</name>
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<bitRange>[30:30]</bitRange>
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<description>Timer-match has fired, cleared by writing 0</description>
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</field>
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<field>
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<name>GPTMR_CTRL_TRIGC</name>
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<bitRange>[31:31]</bitRange>
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<description>Capture-trigger has fired, cleared by writing</description>
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</field>
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</fields>
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</register>
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@ -690,6 +720,12 @@
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<description>Counter register</description>
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<addressOffset>0x08</addressOffset>
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</register>
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<register>
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<name>CAPTURE</name>
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<description>Capture register</description>
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<addressOffset>0x0C</addressOffset>
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<access>read-only</access>
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</register>
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</registers>
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</peripheral>
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