github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 22:27:21 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[README, docs/datasheet] minor typo/layout fixes

Browse source
This commit is contained in:
stnolting 2021-06-04 16:42:01 +02:00
parent 10f223d27c
commit 53c3d41085
2 changed files with 8 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

13
README.md
View file

@ -90,7 +90,7 @@ cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruc
**Timers**
* machine system timer ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V-compatible
* machine system timer ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))
**IO**
@ -101,14 +101,14 @@ cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruc
[TWI / I²C](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi))
* general purpose [GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio) and
[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm)
* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly drive *NeoPixel(TM)* LEDs
* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly drive _NeoPixel(TM)_ LEDs
**SoC Connectivity and Integration**
* 32-bit external bus interface, Wishbone b4 compatible
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd) for AXI4-Lite Master Interface
* alternative [top entities/wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) available providing
* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd) for AXI4-Lite master interface
* alternative [top entities/wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) providing
simplified and/or resolved top entity ports for easy system inegration
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
for tightly-coupled custom co-processor extensions
@ -249,9 +249,8 @@ Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/
| `rv32imc` | 22 008 bytes | 68.97 | **0.6897** | 2981786734 | 611814918 | **4.87** |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 22 008 bytes | 90.91 | **0.9091** | 2265135174 | 611814948 | **3.70** |
:information_source: The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension
(enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration uses a barrel shifter for
CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
:information_source: The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension.
The `FAST_SHIFT_EN` configuration uses a barrel shifter for CPU shift operations.
[[back to top](#The-NEORV32-RISC-V-Processor)]

4
docs/datasheet/on_chip_debugger.adoc
View file

@ -439,7 +439,7 @@ Hence, any CPU access within this address space will succeed.
|=======================
[NOTE]
From the CPU's point of view, the DB is mapped to an _"unused"_ address range within the processor's
From the CPU's point of view, the DM is mapped to an _"unused"_ address range within the processor's
<<_address_space>> right between the bootloader ROM (BOOTROM) and the actual processor-internal IO
space at addresses `0xfffff800` - `0xfffff9ff`
@ -476,7 +476,7 @@ acknowledges the according request.
:sectnums:
=== CPU Debug Mode
The NEORV32 CPU Debug Mode (part of `rtl/core/neorv32_cpu_control.vhd`) is compatible to the "Minimal RISC-V Debug Specification 0.13.2".
The NEORV32 CPU Debug Mode `DB` (part of `rtl/core/neorv32_cpu_control.vhd`) is compatible to the "Minimal RISC-V Debug Specification 0.13.2".
It is enabled/implemented by setting the CPU generic _CPU_EXTENSION_RISCV_DEBUG_ to "true" (done by setting processor
generic _ON_CHIP_DEBUGGER_EN_).
It provides a new operation mode called "debug mode".