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[rtl] tops: replace MTIME by CLINT

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stnolting 2024-12-26 22:26:18 +01:00
parent f4ea5acb0d
commit 53f97f18ef
9 changed files with 17 additions and 16 deletions
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2
rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd
View file

@ -58,7 +58,7 @@ begin
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_CLINT_EN => true, -- implement core local interruptor (CLINT)?
IO_PWM_NUM_CH => IO_PWM_NUM_CH -- number of PWM channels to implement (0..12); 0 = disabled
)
port map (

2
rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd
View file

@ -66,7 +66,7 @@ begin
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_NUM => IO_GPIO_NUM, -- number of GPIO input/output pairs (0..64)
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_CLINT_EN => true, -- implement core local interruptor (CLINT)?
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_PWM_NUM_CH => IO_PWM_NUM_CH -- number of PWM channels to implement (0..12); 0 = disabled
)

2
rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd
View file

@ -93,7 +93,7 @@ begin
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_NUM => IO_GPIO_NUM, -- number of GPIO input/output pairs (0..64)
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_CLINT_EN => true, -- implement core local interruptor (CLINT)?
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => true, -- implement two-wire interface (TWI)?

6
rtl/system_integration/neorv32_litex_core_complex.vhd
View file

@ -88,7 +88,7 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
xcache_en : bool_t;
xcache_nb : natural_t;
xcache_bs : natural_t;
mtime : bool_t;
clint : bool_t;
end record;
-- core complex configurations --
@ -105,7 +105,7 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
xcache_en => ( false, false, true, true ), -- external bus cache enabled
xcache_nb => ( 0, 0, 32, 64 ), -- number of cache blocks (lines), power of two
xcache_bs => ( 0, 0, 32, 32 ), -- size of cache clock (lines) in bytes, power of two
mtime => ( false, true, true, true ) -- RISC-V machine system timer
clint => ( false, true, true, true ) -- RISC-V core local interruptor
);
-- misc --
@ -146,7 +146,7 @@ begin
XBUS_CACHE_NUM_BLOCKS => configs_c.xcache_nb(CONFIG), -- x-cache: number of blocks (min 1), has to be a power of 2
XBUS_CACHE_BLOCK_SIZE => configs_c.xcache_bs(CONFIG), -- x-cache: block size in bytes (min 4), has to be a power of 2
-- Processor peripherals --
IO_MTIME_EN => configs_c.mtime(CONFIG) -- implement machine system timer (MTIME)?
IO_CLINT_EN => configs_c.clint(CONFIG) -- implement core local interruptor (CLINT)?
)
port map (
-- Global control --

9
rtl/system_integration/neorv32_vivado_ip.tcl
View file

@ -135,8 +135,9 @@ proc setup_ip_gui {} {
set_property enablement_dependency {$IO_CFS_EN} [ipx::get_ports cfs_* -of_objects [ipx::current_core]]
set_property enablement_dependency {$IO_NEOLED_EN} [ipx::get_ports neoled_o -of_objects [ipx::current_core]]
set_property enablement_dependency {$XIRQ_EN} [ipx::get_ports xirq_i -of_objects [ipx::current_core]]
set_property enablement_dependency {$IO_MTIME_EN} [ipx::get_ports mtime_time_o -of_objects [ipx::current_core]]
set_property enablement_dependency {!$IO_MTIME_EN} [ipx::get_ports mtime_irq_i -of_objects [ipx::current_core]]
set_property enablement_dependency {$IO_CLINT_EN} [ipx::get_ports mtime_time_o -of_objects [ipx::current_core]]
set_property enablement_dependency {!$IO_CLINT_EN} [ipx::get_ports mtime_irq_i -of_objects [ipx::current_core]]
set_property enablement_dependency {!$IO_CLINT_EN} [ipx::get_ports msw_irq_i -of_objects [ipx::current_core]]
# **************************************************************
@ -311,9 +312,9 @@ proc setup_ip_gui {} {
{ IO_GPIO_OUT_NUM {Number of Outputs} {} {$IO_GPIO_EN} }
}
set group [add_group $page {Machine Timer (MTIME)}]
set group [add_group $page {Core Local Interruptor (CLINT)}]
add_params $group {
{ IO_MTIME_EN {Enable Machine Timer} }
{ IO_CLINT_EN {Enable Core Local Interruptor} }
}
set group [add_group $page {Primary UART (UART0)}]

6
rtl/system_integration/neorv32_vivado_ip.vhd
View file

@ -104,7 +104,7 @@ entity neorv32_vivado_ip is
IO_GPIO_EN : boolean := false;
IO_GPIO_IN_NUM : natural range 1 to 64 := 1; -- variable-sized ports must be at least 0 downto 0; #974
IO_GPIO_OUT_NUM : natural range 1 to 64 := 1;
IO_MTIME_EN : boolean := false;
IO_CLINT_EN : boolean := false;
IO_UART0_EN : boolean := false;
IO_UART0_RX_FIFO : natural range 1 to 2**15 := 1;
IO_UART0_TX_FIFO : natural range 1 to 2**15 := 1;
@ -249,7 +249,7 @@ entity neorv32_vivado_ip is
cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- variable-sized ports must be at least 0 downto 0; #974
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
neoled_o : out std_logic;
-- Machine timer system time (available if IO_MTIME_EN = true) --
-- Machine timer system time (available if IO_CLINT_EN = true) --
mtime_time_o : out std_logic_vector(63 downto 0);
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
xirq_i : in std_logic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- variable-sized ports must be at least 0 downto 0; #974
@ -430,7 +430,7 @@ begin
-- Processor peripherals --
IO_DISABLE_SYSINFO => false,
IO_GPIO_NUM => num_gpio_c,
IO_MTIME_EN => IO_MTIME_EN,
IO_CLINT_EN => IO_CLINT_EN,
IO_UART0_EN => IO_UART0_EN,
IO_UART0_RX_FIFO => IO_UART0_RX_FIFO,
IO_UART0_TX_FIFO => IO_UART0_TX_FIFO,

2
rtl/test_setups/neorv32_test_setup_approm.vhd
View file

@ -57,7 +57,7 @@ begin
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64)
IO_MTIME_EN => true -- implement machine system timer (MTIME)?
IO_CLINT_EN => true -- implement core local interruptor (CLINT)?
)
port map (
-- Global control --

2
rtl/test_setups/neorv32_test_setup_bootloader.vhd
View file

@ -60,7 +60,7 @@ begin
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64)
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_CLINT_EN => true, -- implement core local interruptor (CLINT)?
IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)?
)
port map (

2
rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd
View file

@ -68,7 +68,7 @@ begin
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64)
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_CLINT_EN => true, -- implement core local interruptor (CLINT)?
IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)?
)
port map (