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[rtl] remove core/mem folder
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stnolting
parent
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6 changed files with 2 additions and 441 deletions
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@ -4,20 +4,11 @@
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This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor.
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When creating a new synthesis/simulation project make sure to add all `*.vhd` files from this
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folder to a **new design library** called `neorv32`. The processor's top entity
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is [`neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_top.vhd).
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> [!IMPORTANT]
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> The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/main/rtl/core/mem)
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contains different _platform-agnostic_ VHDL architectures of the processor-internal instruction and
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data memories (IMEM & DMEM). Make sure to add only **one** of each modules to the project's HDL
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file list. However, these default files can also be replaced by optimized technology-specific memory modules.
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folder to a **new design library** called `neorv32`.
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> [!TIP]
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> Two file-list files (`*.f`) are provided that list all required rtl files for the CPU core and
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for the entire processor including their recommended compile order. Make sure to substitute
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the `NEORV32_RTL_PATH_PLACEHOLDER` placeholder by the actual path to _this_ folder (`path/to/neorv32/rtl`).
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The `*.f` files can be re-generated using the provided GHDL bash script (`generate_file_lists.sh`).
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for the entire processor including their recommended compile order.
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See the online documentation for more information:
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https://stnolting.github.io/neorv32/#_file_list_files
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@ -1,18 +0,0 @@
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## Processor Memory Source Files
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This folder provides the architecture-only VHDL sources for the processor-internal memories
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(instruction memory "IMEM", data memory "DMEM"). Different implementations are available, but
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only **one** version of each (IMEM and DMEM) should be added as actual source files.
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For an initial setup the `*.default.vhd` files should be selected. The HDL style for describing
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memories used by these files has proven quite good platform-independence across several FPGA
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architectures and toolchains.
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If synthesis fails to infer block RAM resources from these default files, try the legacy
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`*.legacy.vhd` files, which provide a different HDL style. These files are also intended for
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legacy support of older Intel/Altera Quartus versions (13.0 and older). However, these files
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still do not use platform-specific macros or primitives - so they might also work for other
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FPGAs and toolchains.
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> [!IMPORTANT]
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> Make sure to add the selected files from this folder also to the `neorv32` design library.
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@ -1,82 +0,0 @@
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-- ================================================================================ --
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-- NEORV32 SoC - Processor-Internal Data Memory (DMEM) --
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-- -------------------------------------------------------------------------------- --
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-- Default architecture style. --
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-- -------------------------------------------------------------------------------- --
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-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
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-- Copyright (c) NEORV32 contributors. --
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-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
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-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
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-- SPDX-License-Identifier: BSD-3-Clause --
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-- ================================================================================ --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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architecture neorv32_dmem_rtl of neorv32_dmem is
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-- local signals --
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signal rdata : std_ulogic_vector(31 downto 0);
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signal rden : std_ulogic;
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signal addr : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0);
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-- The memory (RAM) is built from 4 individual byte-wide memories because some synthesis
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-- tools have issues inferring 32-bit memories that provide dedicated byte-enable signals
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-- and/or with multi-dimensional arrays. [NOTE] Read-during-write behavior is irrelevant
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-- as read and write accesses are mutually exclusive.
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signal mem_ram_b0, mem_ram_b1, mem_ram_b2, mem_ram_b3 : mem8_t(0 to DMEM_SIZE/4-1);
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begin
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-- Memory Access --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_access: process(clk_i)
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begin
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if rising_edge(clk_i) then -- no reset to infer block RAM
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
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if (bus_req_i.ben(0) = '1') then -- byte 0
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mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00);
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end if;
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if (bus_req_i.ben(1) = '1') then -- byte 1
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mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08);
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end if;
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if (bus_req_i.ben(2) = '1') then -- byte 2
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mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
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end if;
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if (bus_req_i.ben(3) = '1') then -- byte 3
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mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
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end if;
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end if;
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rdata(07 downto 00) <= mem_ram_b0(to_integer(unsigned(addr)));
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rdata(15 downto 08) <= mem_ram_b1(to_integer(unsigned(addr)));
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rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr)));
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rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr)));
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end if;
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end process mem_access;
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-- word aligned access --
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addr <= bus_req_i.addr(index_size_f(DMEM_SIZE/4)+1 downto 2);
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-- Bus Feedback ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_feedback: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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rden <= '0';
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bus_rsp_o.ack <= '0';
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elsif rising_edge(clk_i) then
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rden <= bus_req_i.stb and (not bus_req_i.rw);
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bus_rsp_o.ack <= bus_req_i.stb;
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end if;
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end process bus_feedback;
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bus_rsp_o.data <= rdata when (rden = '1') else (others => '0'); -- output gate
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bus_rsp_o.err <= '0'; -- no access error possible
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end neorv32_dmem_rtl;
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@ -1,85 +0,0 @@
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-- ================================================================================ --
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-- NEORV32 SoC - Processor-Internal Data Memory (DMEM) --
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-- -------------------------------------------------------------------------------- --
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-- Alternative legacy architecture style. --
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-- -------------------------------------------------------------------------------- --
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-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
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-- Copyright (c) NEORV32 contributors. --
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-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
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-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
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-- SPDX-License-Identifier: BSD-3-Clause --
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-- ================================================================================ --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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architecture neorv32_dmem_rtl of neorv32_dmem is
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-- local signals --
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signal rdata : std_ulogic_vector(31 downto 0);
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signal rden : std_ulogic;
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signal addr, addr_ff : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0);
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-- The memory (RAM) is built from 4 individual byte-wide memories because some synthesis
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-- tools have issues inferring 32-bit memories that provide dedicated byte-enable signals
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-- and/or with multi-dimensional arrays. [NOTE] Read-during-write behavior is irrelevant
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-- as read and write accesses are mutually exclusive.
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signal mem_ram_b0, mem_ram_b1, mem_ram_b2, mem_ram_b3 : mem8_t(0 to DMEM_SIZE/4-1);
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begin
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-- Memory Access --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_access: process(clk_i)
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begin
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if rising_edge(clk_i) then -- no reset to infer block RAM
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addr_ff <= addr;
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
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if (bus_req_i.ben(0) = '1') then -- byte 0
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mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00);
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end if;
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if (bus_req_i.ben(1) = '1') then -- byte 1
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mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08);
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end if;
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if (bus_req_i.ben(2) = '1') then -- byte 2
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mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
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end if;
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if (bus_req_i.ben(3) = '1') then -- byte 3
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mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
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end if;
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end if;
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end if;
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end process mem_access;
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-- sync(!) read - alternative HDL style --
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rdata(07 downto 00) <= mem_ram_b0(to_integer(unsigned(addr_ff)));
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rdata(15 downto 08) <= mem_ram_b1(to_integer(unsigned(addr_ff)));
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rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr_ff)));
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rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr_ff)));
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-- word aligned access --
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addr <= bus_req_i.addr(index_size_f(DMEM_SIZE/4)+1 downto 2);
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-- Bus Feedback ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_feedback: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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rden <= '0';
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bus_rsp_o.ack <= '0';
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elsif rising_edge(clk_i) then
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rden <= bus_req_i.stb and (not bus_req_i.rw);
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bus_rsp_o.ack <= bus_req_i.stb;
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end if;
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end process bus_feedback;
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bus_rsp_o.data <= rdata when (rden = '1') else (others => '0'); -- output gate
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bus_rsp_o.err <= '0'; -- no access error possible
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end neorv32_dmem_rtl;
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-- ================================================================================ --
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-- NEORV32 SoC - Processor-Internal instruction memory (IMEM) --
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-- -------------------------------------------------------------------------------- --
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-- Default architecture style. --
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-- Optionally, this memory implemented as ROM already containing a memory image. --
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-- -------------------------------------------------------------------------------- --
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-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
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-- Copyright (c) NEORV32 contributors. --
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-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
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-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
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-- SPDX-License-Identifier: BSD-3-Clause --
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-- ================================================================================ --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
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architecture neorv32_imem_rtl of neorv32_imem is
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-- local signals --
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signal rdata : std_ulogic_vector(31 downto 0);
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signal rden : std_ulogic;
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signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
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-- application (image) size in bytes --
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constant imem_app_size_c : natural := (application_init_image'length)*4;
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-- ROM - initialized with executable code --
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constant mem_rom_c : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4);
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-- The memory (RAM) is built from 4 individual byte-wide memories because some synthesis
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-- tools have issues inferring 32-bit memories that provide dedicated byte-enable signals
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-- and/or with multi-dimensional arrays. [NOTE] Read-during-write behavior is irrelevant
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-- as read and write accesses are mutually exclusive.
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signal mem_ram_b0, mem_ram_b1, mem_ram_b2, mem_ram_b3 : mem8_t(0 to IMEM_SIZE/4-1);
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert false report
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"[NEORV32] Implementing DEFAULT processor-internal IMEM as " &
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cond_sel_string_f(IMEM_AS_IROM, "pre-initialized ROM.", "blank RAM.") severity note;
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assert not ((IMEM_AS_IROM = true) and (imem_app_size_c > IMEM_SIZE)) report
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"[NEORV32] Application (image = " & natural'image(imem_app_size_c) &
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" bytes) does not fit into processor-internal IMEM (ROM = " & natural'image(IMEM_SIZE) & " bytes)!" severity error;
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-- Implement IMEM as pre-initialized ROM --------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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imem_rom:
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if (IMEM_AS_IROM = true) generate
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mem_access: process(clk_i)
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begin
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if rising_edge(clk_i) then -- no reset to infer block RAM
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rdata <= mem_rom_c(to_integer(unsigned(addr)));
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end if;
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end process mem_access;
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end generate;
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-- word aligned access --
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addr <= bus_req_i.addr(index_size_f(IMEM_SIZE/4)+1 downto 2);
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-- Implement IMEM as non-initialized RAM --------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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imem_ram:
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if (IMEM_AS_IROM = false) generate
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mem_access: process(clk_i)
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begin
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if rising_edge(clk_i) then -- no reset to infer block RAM
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
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if (bus_req_i.ben(0) = '1') then -- byte 0
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mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00);
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end if;
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if (bus_req_i.ben(1) = '1') then -- byte 1
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mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08);
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end if;
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if (bus_req_i.ben(2) = '1') then -- byte 2
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mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
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end if;
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if (bus_req_i.ben(3) = '1') then -- byte 3
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mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
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end if;
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end if;
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rdata(07 downto 00) <= mem_ram_b0(to_integer(unsigned(addr)));
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rdata(15 downto 08) <= mem_ram_b1(to_integer(unsigned(addr)));
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rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr)));
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rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr)));
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end if;
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end process mem_access;
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end generate;
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-- Bus Feedback ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_feedback: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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rden <= '0';
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bus_rsp_o.ack <= '0';
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elsif rising_edge(clk_i) then
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rden <= bus_req_i.stb and (not bus_req_i.rw);
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if (IMEM_AS_IROM = true) then
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bus_rsp_o.ack <= bus_req_i.stb and (not bus_req_i.rw); -- read-only!
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else
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bus_rsp_o.ack <= bus_req_i.stb;
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end if;
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end if;
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end process bus_feedback;
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bus_rsp_o.data <= rdata when (rden = '1') else (others => '0'); -- output gate
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bus_rsp_o.err <= '0'; -- no access error possible
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end neorv32_imem_rtl;
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@ -1,124 +0,0 @@
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-- ================================================================================ --
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-- NEORV32 SoC - Processor-Internal Instruction Memory (IMEM); Legacy Style --
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-- -------------------------------------------------------------------------------- --
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-- Alternative legacy architecture style. --
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-- Optionally, this memory implemented as ROM already containing a memory image. --
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-- -------------------------------------------------------------------------------- --
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-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
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||||
-- Copyright (c) NEORV32 contributors. --
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-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
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-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
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-- SPDX-License-Identifier: BSD-3-Clause --
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-- ================================================================================ --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
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architecture neorv32_imem_rtl of neorv32_imem is
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-- local signals --
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signal rdata : std_ulogic_vector(31 downto 0);
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signal rden : std_ulogic;
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signal addr, addr_ff : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
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-- application (image) size in bytes --
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constant imem_app_size_c : natural := (application_init_image'length)*4;
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-- ROM - initialized with executable code --
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constant mem_rom_c : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4);
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-- The memory (RAM) is built from 4 individual byte-wide memories because some synthesis
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-- tools have issues inferring 32-bit memories that provide dedicated byte-enable signals
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-- and/or with multi-dimensional arrays. [NOTE] Read-during-write behavior is irrelevant
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-- as read and write accesses are mutually exclusive.
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signal mem_ram_b0, mem_ram_b1, mem_ram_b2, mem_ram_b3 : mem8_t(0 to IMEM_SIZE/4-1);
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert false report
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"[NEORV32] Implementing LEGACY processor-internal IMEM as " &
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cond_sel_string_f(IMEM_AS_IROM, "pre-initialized ROM.", "blank RAM.") severity note;
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assert not ((IMEM_AS_IROM = true) and (imem_app_size_c > IMEM_SIZE)) report
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"[NEORV32] Application (image = " & natural'image(imem_app_size_c) &
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" bytes) does not fit into processor-internal IMEM (ROM = " & natural'image(IMEM_SIZE) & " bytes)!" severity error;
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|
||||
-- Implement IMEM as pre-initialized ROM --------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
imem_rom:
|
||||
if (IMEM_AS_IROM = true) generate
|
||||
mem_access: process(clk_i)
|
||||
begin
|
||||
if rising_edge(clk_i) then -- no reset to infer block RAM
|
||||
rdata <= mem_rom_c(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process mem_access;
|
||||
end generate;
|
||||
|
||||
-- word aligned access --
|
||||
addr <= bus_req_i.addr(index_size_f(IMEM_SIZE/4)+1 downto 2);
|
||||
|
||||
|
||||
-- Implement IMEM as non-initialized RAM --------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
imem_ram:
|
||||
if (IMEM_AS_IROM = false) generate
|
||||
mem_access: process(clk_i)
|
||||
begin
|
||||
if rising_edge(clk_i) then
|
||||
addr_ff <= addr;
|
||||
if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then -- no reset to infer block RAM
|
||||
if (bus_req_i.ben(0) = '1') then -- byte 0
|
||||
mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00);
|
||||
end if;
|
||||
if (bus_req_i.ben(1) = '1') then -- byte 1
|
||||
mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08);
|
||||
end if;
|
||||
if (bus_req_i.ben(2) = '1') then -- byte 2
|
||||
mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
|
||||
end if;
|
||||
if (bus_req_i.ben(3) = '1') then -- byte 3
|
||||
mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process mem_access;
|
||||
|
||||
-- sync(!) read - alternative HDL style --
|
||||
rdata(07 downto 00) <= mem_ram_b0(to_integer(unsigned(addr_ff)));
|
||||
rdata(15 downto 08) <= mem_ram_b1(to_integer(unsigned(addr_ff)));
|
||||
rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr_ff)));
|
||||
rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr_ff)));
|
||||
end generate;
|
||||
|
||||
|
||||
-- Bus Feedback ---------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
bus_feedback: process(rstn_i, clk_i)
|
||||
begin
|
||||
if (rstn_i = '0') then
|
||||
rden <= '0';
|
||||
bus_rsp_o.ack <= '0';
|
||||
elsif rising_edge(clk_i) then
|
||||
rden <= bus_req_i.stb and (not bus_req_i.rw);
|
||||
if (IMEM_AS_IROM = true) then
|
||||
bus_rsp_o.ack <= bus_req_i.stb and (not bus_req_i.rw); -- read-only!
|
||||
else
|
||||
bus_rsp_o.ack <= bus_req_i.stb;
|
||||
end if;
|
||||
end if;
|
||||
end process bus_feedback;
|
||||
|
||||
bus_rsp_o.data <= rdata when (rden = '1') else (others => '0'); -- output gate
|
||||
bus_rsp_o.err <= '0'; -- no access error possible
|
||||
|
||||
|
||||
end neorv32_imem_rtl;
|
||||
Loading…
Add table
Add a link
Reference in a new issue