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[docs] minor table format fixing
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stnolting 2024-10-17 22:50:38 +02:00
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docs/datasheet/soc.adoc
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@ -79,7 +79,7 @@ clock domain also using registers. However, for ASIC implementations it is recom
to all inputs and output so the synthesis tool can insert an explicit IO (boundary) scan chain.
.NEORV32 Processor Signal List
[cols="<3,^1,^1,^1,<8"]
[cols="<4,^2,^2,^2,<7"]
[options="header",grid="rows"]
|=======================
| Name | Width | Direction | Default | Description