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[docs] add attrs.adoc and attrs.main.adoc

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umarcor 2021-06-08 10:18:09 +02:00
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:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.5.6.0
:doctype: book
:sectnums:
:stem:
:reproducible:
:listing-caption: Listing
:toclevels: 4
:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
:favicon: img/icon.png

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:icons: image
:iconsdir: ../icons
:imagesdir: ../figures
:toc: macro
:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
// Uncomment next line to set page size (default is A4)
//:pdf-page-size: Letter

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docs/datasheet/index.adoc
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= The NEORV32 RISC-V Processor: Datasheet
include::../attrs.adoc[]
:title: [Datasheet] The NEORV32 RISC-V Processor
:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.5.6.0
:doctype: book
:sectnums:
:icons: font
:imagesdir: img
:stem:
:reproducible:
:listing-caption: Listing
:toc: left
:toclevels: 4
:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
:favicon: img/icon.png

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docs/datasheet/main.adoc
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@ -1,21 +1,6 @@
= The NEORV32 RISC-V Processor: Datasheet
:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.5.6.0
:doctype: book
:sectnums:
:icons: image
:iconsdir: ../icons
:imagesdir: ../figures
:stem:
:reproducible:
:listing-caption: Listing
:toc: macro
:toclevels: 4
:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
// Uncomment next line to set page size (default is A4)
//:pdf-page-size: Letter
include::../attrs.adoc[]
include::../attrs.main.adoc[]
<<<

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docs/userguide/index.adoc
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@ -1,18 +1,9 @@
= The NEORV32 RISC-V Processor: User Guide
include::../attrs.adoc[]
:title: [User Guide] The NEORV32 RISC-V Processor
:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.5.6.0
:doctype: book
:sectnums:
:icons: font
:imagesdir: ../img
:stem:
:reproducible:
:listing-caption: Listing
:toc: left
:toclevels: 4
:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
:favicon: ../img/icon.png

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docs/userguide/main.adoc
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@ -1,21 +1,6 @@
= The NEORV32 RISC-V Processor: User Guide
:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.5.6.0
:doctype: book
:sectnums:
:icons: image
:iconsdir: ../icons
:imagesdir: ../figures
:stem:
:reproducible:
:listing-caption: Listing
:toc: macro
:toclevels: 4
:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
// Uncomment next line to set page size (default is A4)
//:pdf-page-size: Letter
include::../attrs.adoc[]
include::../attrs.main.adoc[]
<<<