mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-19 11:55:05 -04:00
[rtl] minor comment edits
This commit is contained in:
stnolting
parent
cb9679aeaf
commit
5c23e23d9b
3 changed files with 49 additions and 50 deletions
|
|
@ -667,19 +667,19 @@ begin
|
|||
-- ------------------------------------------------------------
|
||||
case csr_addr_v is
|
||||
|
||||
-- user-defined U-mode CFU CSRs --
|
||||
-- NEORV32-specific user-mode CFU CSRs --
|
||||
when csr_cfureg0_c | csr_cfureg1_c | csr_cfureg2_c | csr_cfureg3_c =>
|
||||
csr_valid(2) <= bool_to_ulogic_f(RISCV_ISA_Zxcfu); -- available if CFU implemented
|
||||
|
||||
-- floating-point CSRs --
|
||||
-- floating-point-unit CSRs --
|
||||
when csr_fflags_c | csr_frm_c | csr_fcsr_c =>
|
||||
csr_valid(2) <= bool_to_ulogic_f(RISCV_ISA_Zfinx); -- available if FPU implemented
|
||||
|
||||
-- machine trap setup/handling, environment/information registers, etc. --
|
||||
when csr_mstatus_c | csr_mstatush_c | csr_misa_c | csr_mie_c | csr_mtvec_c |
|
||||
csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mip_c | csr_mtval_c |
|
||||
csr_mtinst_c | csr_mcountinhibit_c | csr_mvendorid_c | csr_marchid_c | csr_mimpid_c |
|
||||
csr_mhartid_c | csr_mconfigptr_c | csr_mxisa_c | csr_mxiccsreg_c | csr_mxiccdata_c =>
|
||||
when csr_mstatus_c | csr_mstatush_c | csr_misa_c | csr_mie_c | csr_mtvec_c |
|
||||
csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mip_c | csr_mtval_c |
|
||||
csr_mtinst_c | csr_mcountinhibit_c | csr_mvendorid_c | csr_marchid_c | csr_mimpid_c |
|
||||
csr_mhartid_c | csr_mconfigptr_c | csr_mxisa_c | csr_mxiccsreg_c | csr_mxiccdata_c =>
|
||||
csr_valid(2) <= '1'; -- always implemented
|
||||
|
||||
-- machine-controlled user-mode CSRs --
|
||||
|
|
@ -1400,7 +1400,7 @@ begin
|
|||
end if;
|
||||
|
||||
-- --------------------------------------------------------------------
|
||||
-- custom functions unit
|
||||
-- custom functions unit (NEORV32-specific)
|
||||
-- --------------------------------------------------------------------
|
||||
when csr_cfureg0_c | csr_cfureg1_c | csr_cfureg2_c | csr_cfureg3_c =>
|
||||
if RISCV_ISA_Zxcfu then
|
||||
|
|
@ -1408,7 +1408,7 @@ begin
|
|||
end if;
|
||||
|
||||
-- --------------------------------------------------------------------
|
||||
-- inter-core communication
|
||||
-- inter-core communication (NEORV32-specific)
|
||||
-- --------------------------------------------------------------------
|
||||
when csr_mxiccsreg_c | csr_mxiccdata_c =>
|
||||
csr.rdata <= xcsr_rdata_i; -- implemented externally
|
||||
|
|
@ -1569,45 +1569,45 @@ begin
|
|||
when csr_tinfo_c => if RISCV_ISA_Sdtrig then csr.rdata <= x"01000006"; end if; -- trigger information (Sdtrig v1.0; mcontrol6-type only)
|
||||
|
||||
-- --------------------------------------------------------------------
|
||||
-- NEORV32-specific (RISC-V "custom") read-only machine-mode CSRs
|
||||
-- NEORV32-specific read-only machine-mode CSRs
|
||||
-- --------------------------------------------------------------------
|
||||
-- machine extended ISA extensions information --
|
||||
when csr_mxisa_c =>
|
||||
-- extended ISA (sub-)extensions --
|
||||
csr.rdata(0) <= '1'; -- Zicsr: CSR access (always enabled)
|
||||
csr.rdata(1) <= '1'; -- Zifencei: instruction stream sync. (always enabled)
|
||||
csr.rdata(2) <= bool_to_ulogic_f(RISCV_ISA_Zmmul); -- Zmmul: mul/div
|
||||
csr.rdata(3) <= bool_to_ulogic_f(RISCV_ISA_Zxcfu); -- Zxcfu: custom RISC-V instructions
|
||||
csr.rdata(4) <= bool_to_ulogic_f(RISCV_ISA_Zkt); -- Zkt: data independent execution latency
|
||||
csr.rdata(5) <= bool_to_ulogic_f(RISCV_ISA_Zfinx); -- Zfinx: FPU using x registers
|
||||
csr.rdata(6) <= bool_to_ulogic_f(RISCV_ISA_Zicond); -- Zicond: integer conditional operations
|
||||
csr.rdata(7) <= bool_to_ulogic_f(RISCV_ISA_Zicntr); -- Zicntr: base counters
|
||||
csr.rdata(8) <= bool_to_ulogic_f(RISCV_ISA_Smpmp); -- Smpmp: physical memory protection
|
||||
csr.rdata(9) <= bool_to_ulogic_f(RISCV_ISA_Zihpm); -- Zihpm: hardware performance monitors
|
||||
csr.rdata(10) <= bool_to_ulogic_f(RISCV_ISA_Sdext); -- Sdext: RISC-V external debug
|
||||
csr.rdata(11) <= bool_to_ulogic_f(RISCV_ISA_Sdtrig); -- Sdtrig: trigger module
|
||||
csr.rdata(12) <= bool_to_ulogic_f(RISCV_ISA_Zbkx); -- Zbkx: cryptography crossbar permutation
|
||||
csr.rdata(13) <= bool_to_ulogic_f(RISCV_ISA_Zknd); -- Zknd: cryptography NIST AES decryption
|
||||
csr.rdata(14) <= bool_to_ulogic_f(RISCV_ISA_Zkne); -- Zkne: cryptography NIST AES encryption
|
||||
csr.rdata(15) <= bool_to_ulogic_f(RISCV_ISA_Zknh); -- Zknh: cryptography NIST hash functions
|
||||
csr.rdata(16) <= bool_to_ulogic_f(RISCV_ISA_Zbkb); -- Zbkb: bit manipulation instructions for cryptography
|
||||
csr.rdata(17) <= bool_to_ulogic_f(RISCV_ISA_Zbkc); -- Zbkc: carry-less multiplication for cryptography
|
||||
csr.rdata(18) <= bool_to_ulogic_f(RISCV_ISA_Zkn); -- Zkn: NIST algorithm suite
|
||||
csr.rdata(19) <= bool_to_ulogic_f(RISCV_ISA_Zksh); -- Zksh: ShangMi hash functions
|
||||
csr.rdata(20) <= bool_to_ulogic_f(RISCV_ISA_Zksed); -- Zksed: ShangMi block ciphers
|
||||
csr.rdata(21) <= bool_to_ulogic_f(RISCV_ISA_Zks); -- Zks: ShangMi algorithm suite
|
||||
csr.rdata(22) <= bool_to_ulogic_f(RISCV_ISA_Zba); -- Zba: shifted-add bit-manipulation
|
||||
csr.rdata(23) <= bool_to_ulogic_f(RISCV_ISA_Zbb); -- Zbb: basic bit-manipulation
|
||||
csr.rdata(24) <= bool_to_ulogic_f(RISCV_ISA_Zbs); -- Zbs: single-bit bit-manipulation
|
||||
csr.rdata(25) <= bool_to_ulogic_f(RISCV_ISA_Zaamo); -- Zaamo: atomic memory operations
|
||||
csr.rdata(26) <= bool_to_ulogic_f(RISCV_ISA_Zalrsc); -- Zalrsc: reservation-set operations
|
||||
csr.rdata(27) <= '0'; -- reserved
|
||||
csr.rdata(0) <= '1'; -- Zicsr: CSR access (always enabled)
|
||||
csr.rdata(1) <= '1'; -- Zifencei: instruction stream sync. (always enabled)
|
||||
csr.rdata(2) <= bool_to_ulogic_f(RISCV_ISA_Zmmul); -- Zmmul: mul/div
|
||||
csr.rdata(3) <= bool_to_ulogic_f(RISCV_ISA_Zxcfu); -- Zxcfu: custom RISC-V instructions
|
||||
csr.rdata(4) <= bool_to_ulogic_f(RISCV_ISA_Zkt); -- Zkt: data independent execution latency
|
||||
csr.rdata(5) <= bool_to_ulogic_f(RISCV_ISA_Zfinx); -- Zfinx: FPU using x registers
|
||||
csr.rdata(6) <= bool_to_ulogic_f(RISCV_ISA_Zicond); -- Zicond: integer conditional operations
|
||||
csr.rdata(7) <= bool_to_ulogic_f(RISCV_ISA_Zicntr); -- Zicntr: base counters
|
||||
csr.rdata(8) <= bool_to_ulogic_f(RISCV_ISA_Smpmp); -- Smpmp: physical memory protection
|
||||
csr.rdata(9) <= bool_to_ulogic_f(RISCV_ISA_Zihpm); -- Zihpm: hardware performance monitors
|
||||
csr.rdata(10) <= bool_to_ulogic_f(RISCV_ISA_Sdext); -- Sdext: RISC-V external debug
|
||||
csr.rdata(11) <= bool_to_ulogic_f(RISCV_ISA_Sdtrig); -- Sdtrig: trigger module
|
||||
csr.rdata(12) <= bool_to_ulogic_f(RISCV_ISA_Zbkx); -- Zbkx: cryptography crossbar permutation
|
||||
csr.rdata(13) <= bool_to_ulogic_f(RISCV_ISA_Zknd); -- Zknd: cryptography NIST AES decryption
|
||||
csr.rdata(14) <= bool_to_ulogic_f(RISCV_ISA_Zkne); -- Zkne: cryptography NIST AES encryption
|
||||
csr.rdata(15) <= bool_to_ulogic_f(RISCV_ISA_Zknh); -- Zknh: cryptography NIST hash functions
|
||||
csr.rdata(16) <= bool_to_ulogic_f(RISCV_ISA_Zbkb); -- Zbkb: bit manipulation instructions for cryptography
|
||||
csr.rdata(17) <= bool_to_ulogic_f(RISCV_ISA_Zbkc); -- Zbkc: carry-less multiplication for cryptography
|
||||
csr.rdata(18) <= bool_to_ulogic_f(RISCV_ISA_Zkn); -- Zkn: NIST algorithm suite
|
||||
csr.rdata(19) <= bool_to_ulogic_f(RISCV_ISA_Zksh); -- Zksh: ShangMi hash functions
|
||||
csr.rdata(20) <= bool_to_ulogic_f(RISCV_ISA_Zksed); -- Zksed: ShangMi block ciphers
|
||||
csr.rdata(21) <= bool_to_ulogic_f(RISCV_ISA_Zks); -- Zks: ShangMi algorithm suite
|
||||
csr.rdata(22) <= bool_to_ulogic_f(RISCV_ISA_Zba); -- Zba: shifted-add bit-manipulation
|
||||
csr.rdata(23) <= bool_to_ulogic_f(RISCV_ISA_Zbb); -- Zbb: basic bit-manipulation
|
||||
csr.rdata(24) <= bool_to_ulogic_f(RISCV_ISA_Zbs); -- Zbs: single-bit bit-manipulation
|
||||
csr.rdata(25) <= bool_to_ulogic_f(RISCV_ISA_Zaamo); -- Zaamo: atomic memory operations
|
||||
csr.rdata(26) <= bool_to_ulogic_f(RISCV_ISA_Zalrsc); -- Zalrsc: reservation-set operations
|
||||
csr.rdata(27) <= '0'; -- reserved
|
||||
-- tuning options --
|
||||
csr.rdata(28) <= bool_to_ulogic_f(CPU_RF_HW_RST_EN); -- full hardware reset of register file
|
||||
csr.rdata(29) <= bool_to_ulogic_f(CPU_FAST_MUL_EN); -- DSP-based multiplication (M extensions only)
|
||||
csr.rdata(30) <= bool_to_ulogic_f(CPU_FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters)
|
||||
csr.rdata(28) <= bool_to_ulogic_f(CPU_RF_HW_RST_EN); -- full hardware reset of register file
|
||||
csr.rdata(29) <= bool_to_ulogic_f(CPU_FAST_MUL_EN); -- DSP-based multiplication (M extensions only)
|
||||
csr.rdata(30) <= bool_to_ulogic_f(CPU_FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters)
|
||||
-- misc --
|
||||
csr.rdata(31) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
|
||||
csr.rdata(31) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
|
||||
|
||||
-- --------------------------------------------------------------------
|
||||
-- undefined/unavailable
|
||||
|
|
|
|||
|
|
@ -220,7 +220,7 @@ begin
|
|||
if (fetch.restart = '1') then
|
||||
issue.align <= ctrl_i.pc_nxt(1); -- branch to unaligned address?
|
||||
elsif (ctrl_i.if_ack = '1') then
|
||||
issue.align <= (issue.align and (not issue.alclr)) or issue.alset; -- "rs flip-flop"
|
||||
issue.align <= (issue.align and (not issue.alclr)) or issue.alset; -- alignment "RS flip-flop"
|
||||
end if;
|
||||
end if;
|
||||
end process issue_fsm_sync;
|
||||
|
|
@ -231,7 +231,7 @@ begin
|
|||
issue.alset <= '0';
|
||||
issue.alclr <= '0';
|
||||
issue.valid <= "00";
|
||||
-- start with LOW half-word --
|
||||
-- start at LOW half-word --
|
||||
if (issue.align = '0') then
|
||||
issue.error <= ipb.rdata(0)(16);
|
||||
if (ipb.rdata(0)(1 downto 0) /= "11") then -- compressed, use IPB(0) entry
|
||||
|
|
@ -244,7 +244,7 @@ begin
|
|||
issue.instr <= ipb.rdata(1)(15 downto 0) & ipb.rdata(0)(15 downto 0);
|
||||
issue.compr <= '0';
|
||||
end if;
|
||||
-- start with HIGH half-word --
|
||||
-- start at HIGH half-word --
|
||||
else
|
||||
issue.error <= ipb.rdata(1)(16);
|
||||
if (ipb.rdata(1)(1 downto 0) /= "11") then -- compressed, use IPB(1) entry
|
||||
|
|
|
|||
|
|
@ -47,8 +47,8 @@ architecture neorv32_twd_rtl of neorv32_twd is
|
|||
constant ctrl_irq_rx_avail_c : natural := 11; -- r/w: IRQ if RX FIFO data available
|
||||
constant ctrl_irq_rx_full_c : natural := 12; -- r/w: IRQ if RX FIFO full
|
||||
constant ctrl_irq_tx_empty_c : natural := 13; -- r/w: IRQ if TX FIFO empty
|
||||
constant ctrl_tx_dummy_en_c : natural := 14; -- r/w: enable sending tx_dummy (last sent byte) when fifo is empty
|
||||
constant ctrl_hide_read_c : natural := 15; -- r/w: generate NACK ony READ-access when TX FIFO is empty
|
||||
constant ctrl_tx_dummy_en_c : natural := 14; -- r/w: enable sending tx_dummy (last sent byte) when FIFO is empty
|
||||
constant ctrl_hide_read_c : natural := 15; -- r/w: generate NACK on READ-access when TX FIFO is empty
|
||||
constant ctrl_rx_fifo_size0_c : natural := 16; -- r/-: log2(RX_FIFO size), bit 0 (LSB)
|
||||
constant ctrl_rx_fifo_size3_c : natural := 19; -- r/-: log2(RX_FIFO size), bit 3 (MSB)
|
||||
constant ctrl_tx_fifo_size0_c : natural := 20; -- r/-: log2(TX_FIFO size), bit 0 (LSB)
|
||||
|
|
@ -247,10 +247,9 @@ begin
|
|||
end process tx_backup;
|
||||
|
||||
-- TX Data
|
||||
engine.rdata <=
|
||||
tx_fifo.rdata when (tx_fifo.avail = '1') else -- read TX FIFO when available
|
||||
tx_dummy when (ctrl.tx_dummy_en = '1') -- read 'tx_dummy' when TX FIFO is drained and tx_dummy_en enabled
|
||||
else (others => '1'); -- read '1' when TX FIFO is drained and tx_dummy_en disabled
|
||||
engine.rdata <= tx_fifo.rdata when (tx_fifo.avail = '1') else -- read TX FIFO when available
|
||||
tx_dummy when (ctrl.tx_dummy_en = '1') else -- read 'tx_dummy' when TX FIFO is drained and tx_dummy_en enabled
|
||||
(others => '1'); -- read '1' when TX FIFO is drained and tx_dummy_en disabled
|
||||
|
||||
|
||||
-- RX FIFO --
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue