⚠️ Rework SYSINFO module (#659)

2025-04-24 22:27:21 -04:00 · 2023-07-28 13:30:19 +02:00 · 2023-07-28 13:30:19 +02:00 · 609f00d727
commit 609f00d727
parent 2e99380297 9563389393
29 changed files with 446 additions and 502 deletions
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 28.07.2023 | 1.8.7.3 | :warning: reworked **SYSINFO** module; clean-up address space layout; clean-up assertion notes; [#659](https://github.com/stnolting/neorv32/pull/659) |
 | 27.07.2023 | 1.8.7.2 | :bug: make sure that IMEM/DMEM size is always a power of two; [#658](https://github.com/stnolting/neorv32/pull/658) |
 | 27.07.2023 | 1.8.7.1 | :warning: remove `CUSTOM_ID` generic; cleanup and re-layout `NEORV32_SYSINFO.SOC` bits; (:bug:) fix gateway's generics (`positive` -> `natural` as these generics are allowed to be zero); [#657](https://github.com/stnolting/neorv32/pull/657) |
 | 26.07.2023 | [**:rocket:1.8.7**](https://github.com/stnolting/neorv32/releases/tag/v1.8.7) | **New release** |
--- a/docs/datasheet/cpu.adoc
+++ b/docs/datasheet/cpu.adoc
@ -166,9 +166,7 @@ CPU back-end for actual execution. Execution is conducted by a state-machine tha
 includes the <<_control_and_status_registers_csrs>> as well as the trap controller.


-// ####################################################################################################################
-:sectnums:
-=== Sleep Mode
+==== Sleep Mode

 The NEORV32 CPU provides a single sleep mode that can be entered to power-down the core reducing dynamic
 power consumption. Sleep mode in entered by executing the `wfi` instruction. When in sleep mode, all CPU-internal
@ -184,9 +182,7 @@ The CPU automatically wakes up from sleep mode if a debug session is started via
 a simple `nop` when the CPU is _in_ debug-mode or during single-stepping.


-// ####################################################################################################################
-:sectnums:
-=== Full Virtualization
+==== Full Virtualization

 Just like the RISC-V ISA, the NEORV32 aims to provide _maximum virtualization_ capabilities on CPU and SoC level to
 allow a high standard of **execution safety**. The CPU supports **all** traps specified by the official RISC-V
@ -197,6 +193,115 @@ out-of-order operations that might have to be reverted). This allows a defined a
 at any time improving overall execution safety.


+<<<
+// ####################################################################################################################
+:sectnums:
+=== Bus Interface
+
+The NEORV32 CPU provides separated instruction fetch and data access interfaces making it a **Harvard Architecture**:
+the instruction fetch interface (`i_bus_*` signals) is used for fetching instructions and the data access interface
+(`d_bus_*` signals) is used to access data via load and store operations. Each of these interfaces can access an address
+space of up to 2^32^ bytes (4GB).
+
+The bus interface uses two custom interface types: `bus_req_t` is used to propagate the bus access **requests**. These
+signals are driven by the _accessing_ device (i.e. the CPU core). `bus_rsp_t` is used to return the bus **response** and
+is driven by the _accessed_ device or bus system (i.e. a processor-internal memory or IO device).
+
+.Bus Interface - Request Bus (`bus_req_t`)
+[cols="^1,^1,<6"]
+[options="header",grid="rows"]
+|=======================
+| Signal | Width | Description
+| `addr` |    32 | Access address (byte addressing)
+| `data` |    32 | Write data
+| `ben`  |     4 | Byte-enable for each byte in `data`
+| `we`   |     1 | **Write** request trigger (single-shot)
+| `re`   |     1 | **Read** request trigger (single-shot)
+| `src`  |     1 | Access source (`0` = instruction fetch, `1` = load/store)
+| `priv` |     1 | Set if privileged (M-mode) access
+| `rvso` |     1 | Set if current access is a reservation-set operation (atomic `lr` or `sc` instruction)
+|=======================
+
+.Bus Interface - Response Bus (`bus_rsp_t`)
+[cols="^1,^1,<6"]
+[options="header",grid="rows"]
+|=======================
+| Signal | Width | Description
+| `data` |    32 | Read data (single-shot)
+| `ack`  |     1 | Transfer acknowledge / success (single-shot)
+| `err`  |     1 | Transfer error / fail (single-shot)
+|=======================
+
+.Processor Bus System
+[NOTE]
+This type of bus system is used for used for the entire NEORV32 processor to construct the <<_address_space>>.
+
+
+:sectnums:
+==== Bus Interface Protocol
+
+Bus transaction are entirely triggered by the request bus. A new bus request is initiated either by the `re` signal
+(= read request) or by the `we` signal (= write request). These signals are mutually exclusive. In case of a request,
+the according signal is high for exactly one clock cycle. The transaction is completed when the accessed device returns
+a response via the response interface: `ack` is high for exactly one cycle if the transaction was completed successfully.
+`err` is high for exactly one cycle if the transaction failed to complete. These two signals are also mutually exclusive.
+In case of a read access the read data is returned together with the `ack` signal. Otherwise, the return data signal is
+kept at all-zero allowing wired-or interconnection of all response buses.
+
+The figure below shows three exemplary bus accesses:
+
+[start=1]
+. A read access to address `A_addr` returning `rdata` after several cycles (slow response; `ACK` arrives after several cycles).
+. A write access to address `B_addr` writing `wdata` (fastest response; `ACK` arrives right in the next cycle).
+. A failing read access to address `C_addr` (slow response; `ERR` arrives after several cycles).
+
+.Three Exemplary Bus Transactions
+image::bus_interface.png[700]
+
+.Signal State
+[NOTE]
+All signals of the request bus interface (except for the read/write transfer triggers)
+remain stable until the bus access is completed.
+
+
+:sectnums:
+==== Atomic Accesses
+
+The load-reservate (`lr.w`) and store-conditional (`sc.w`) instructions from the <<_a_isa_extension>> execute as standard
+load/store bus transactions but with the `rvso` ("reservation set operation") signal being set. It is the task of the
+<<_reservation_set_controller>> to handle these LR/SC bus transactions accordingly.
+
+.Reservation Set Controller
+[NOTE]
+See section <<_address_space>> / <<_reservation_set_controller>> for more information.
+
+.Read-Modify-Write Operations
+[IMPORTANT]
+Read-modify-write operations (line an atomic swap / `amoswap.w`) are **not** supported. However, the NEORV32
+<<_core_libraries>> provide an emulation wrapper for those unsupported instructions that is
+based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
+
+The figure below shows three exemplary bus accesses. For easier understanding the current state of the reservation set
+is added as `rvs_valid` signal.
+
+[start=1]
+. A load-reservate (LR) instruction using `addr` as address. This instruction returns the loaded data `rdata` and also
+registers a reservation for the address `addr` (`rvs_valid` becomes set).
+. A store-conditional (SC) instruction attempts to write `wdata1` to `addr`. This SC operation **succeeds**, so `wdata1`
+is actually written to `addr`. The successful operation is indicated by a 1 being returned via the `rsp.data` signal
+together with the `ack`. As the LR/SC is completed the registered reservation is invalidated (`rvs_valid` becomes cleared).
+. Another store-conditional (SC) instruction attempts to write `wdata2` to `addr`. As the reservation set is already invalidated
+(`rvs_valid` is `0`) the store access fails, so `wdata2` is **not** written to `addr`. The failed operation is indicated by a 0
+being returned via the `rsp.data` signal together with the `ack`.
+
+.Three Exemplary LR/SC Bus Transactions
+image::bus_interface_atomic.png[700]
+
+.SC Status
+[NOTE]
+The normal "load data" mechanism is used to return success/failure of the `sc.w` instruction to the CPU (via `rsp.data`).
+
+
 <<<
 // ####################################################################################################################
 :sectnums:
@ -796,113 +901,3 @@ address misaligned" exception are not resumable in most cases. These exception m
 For 32-bit-only instructions (= no `C` extension) the misaligned instruction exception is raised if bit 1 of the fetch
 address is set (i.e. not on a 32-bit boundary). If the `C` extension is implemented there will never be a misaligned
 instruction exception _at all_. In both cases bit 0 of the program counter (and all related CSRs) is hardwired to zero.
-
-
-
-<<<
-// ####################################################################################################################
-:sectnums:
-==== Bus Interface
-
-The NEORV32 CPU provides separated instruction fetch and data access interfaces making it a **Harvard Architecture**:
-the instruction fetch interface (`i_bus_*` signals) is used for fetching instructions and the data access interface
-(`d_bus_*` signals) is used to access data via load and store operations. Each of these interfaces can access an address
-space of up to 2^32^ bytes (4GB).
-
-The bus interface uses two custom interface types: `bus_req_t` is used to propagate the bus access **requests**. These
-signals are driven by the _accessing_ device (i.e. the CPU core). `bus_rsp_t` is used to return the bus **response** and
-is driven by the _accessed_ device or bus system (i.e. a processor-internal memory or IO device).
-
-.Bus Interface - Request Bus (`bus_req_t`)
-[cols="^1,^1,<6"]
-[options="header",grid="rows"]
-|=======================
-| Signal | Width | Description
-| `addr` |    32 | Access address (byte addressing)
-| `data` |    32 | Write data
-| `ben`  |     4 | Byte-enable for each byte in `data`
-| `we`   |     1 | **Write** request trigger (single-shot)
-| `re`   |     1 | **Read** request trigger (single-shot)
-| `src`  |     1 | Access source (`0` = instruction fetch, `1` = load/store)
-| `priv` |     1 | Set if privileged (M-mode) access
-| `rvso` |     1 | Set if current access is a reservation-set operation (atomic `lr` or `sc` instruction)
-|=======================
-
-.Bus Interface - Response Bus (`bus_rsp_t`)
-[cols="^1,^1,<6"]
-[options="header",grid="rows"]
-|=======================
-| Signal | Width | Description
-| `data` |    32 | Read data (single-shot)
-| `ack`  |     1 | Transfer acknowledge / success (single-shot)
-| `err`  |     1 | Transfer error / fail (single-shot)
-|=======================
-
-.Processor Bus System
-[NOTE]
-This type of bus system is used for used for the entire NEORV32 processor to construct the <<_address_space>>.
-
-
-:sectnums:
-===== Bus Interface Protocol
-
-Bus transaction are entirely triggered by the request bus. A new bus request is initiated either by the `re` signal
-(= read request) or by the `we` signal (= write request). These signals are mutually exclusive. In case of a request,
-the according signal is high for exactly one clock cycle. The transaction is completed when the accessed device returns
-a response via the response interface: `ack` is high for exactly one cycle if the transaction was completed successfully.
-`err` is high for exactly one cycle if the transaction failed to complete. These two signals are also mutually exclusive.
-In case of a read access the read data is returned together with the `ack` signal. Otherwise, the return data signal is
-kept at all-zero allowing wired-or interconnection of all response buses.
-
-The figure below shows three exemplary bus accesses:
-
-[start=1]
-. A read access to address `A_addr` returning `rdata` after several cycles (slow response; `ACK` arrives after several cycles).
-. A write access to address `B_addr` writing `wdata` (fastest response; `ACK` arrives right in the next cycle).
-. A failing read access to address `C_addr` (slow response; `ERR` arrives after several cycles).
-
-.Three Exemplary Bus Transactions
-image::bus_interface.png[700]
-
-.Signal State
-[NOTE]
-All signals of the request bus interface (except for the read/write transfer triggers)
-remain stable until the bus access is completed.
-
-
-:sectnums:
-===== Atomic Accesses
-
-The load-reservate (`lr.w`) and store-conditional (`sc.w`) instructions from the <<_a_isa_extension>> execute as standard
-load/store bus transactions but with the `rvso` ("reservation set operation") signal being set. It is the task of the
-<<_reservation_set_controller>> to handle these LR/SC bus transactions accordingly.
-
-.Reservation Set Controller
-[NOTE]
-See section <<_address_space>> / <<_reservation_set_controller>> for more information.
-
-.Read-Modify-Write Operations
-[IMPORTANT]
-Read-modify-write operations (line an atomic swap / `amoswap.w`) are **not** supported. However, the NEORV32
-<<_core_libraries>> provide an emulation wrapper for those unsupported instructions that is
-based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
-
-The figure below shows three exemplary bus accesses. For easier understanding the current state of the reservation set
-is added as `rvs_valid` signal.
-
-[start=1]
-. A load-reservate (LR) instruction using `addr` as address. This instruction returns the loaded data `rdata` and also
-registers a reservation for the address `addr` (`rvs_valid` becomes set).
-. A store-conditional (SC) instruction attempts to write `wdata1` to `addr`. This SC operation **succeeds**, so `wdata1`
-is actually written to `addr`. The successful operation is indicated by a 1 being returned via the `rsp.data` signal
-together with the `ack`. As the LR/SC is completed the registered reservation is invalidated (`rvs_valid` becomes cleared).
-. Another store-conditional (SC) instruction attempts to write `wdata2` to `addr`. As the reservation set is already invalidated
-(`rvs_valid` is `0`) the store access fails, so `wdata2` is **not** written to `addr`. The failed operation is indicated by a 0
-being returned via the `rsp.data` signal together with the `ack`.
-
-.Three Exemplary LR/SC Bus Transactions
-image::bus_interface_atomic.png[700]
-
-.SC Status
-[NOTE]
-The normal "load data" mechanism is used to return success/failure of the `sc.w` instruction to the CPU (via `rsp.data`).
--- a/docs/datasheet/soc.adoc
+++ b/docs/datasheet/soc.adoc
@ -468,12 +468,12 @@ image::address_space.png[900]
 [options="header",grid="rows"]
 |=======================
 | # | Region                      | PMAs  | Description
-| 1 | Instruction address space   | `rwx` | For instructions (=code) and constants. A configurable section of this address space can used by the internal <<_instruction_memory_imem>>.
-| 2 | Data address space          | `rwx` | For application runtime data (heap, stack, etc.). A configurable section of this address space can be used by the internal <<_data_memory_dmem>>). Code can also be executed from data memory.
+| 1 | Internal IMEM address space | `rwx` | For instructions (=code) and constants; mapped to the internal <<_instruction_memory_imem>>.
+| 2 | Internal DMEM address space | `rwx` | For application runtime data (heap, stack, etc.); mapped to the internal <<_data_memory_dmem>>).
 | 3 | Memory-mapped XIP flash     | `r-x` | Memory-mapped access to the <<_execute_in_place_module_xip>> SPI flash.
 | 4 | Bootloader address space    | `r-x` | Read-only memory for the internal <<_bootloader_rom_bootrom>> containing the default <<_bootloader>>.
 | 5 | IO/peripheral address space | `rwx` | Processor-internal peripherals / IO devices.
-| 6 | The "void"                  | `rwx` | Unmapped address space. All accesses to this region(s) are redirected to the <<_processor_external_memory_interface_wishbone>>.
+| 6 | The "**void**"              | `rwx` | Unmapped address space. All accesses to this region(s) are redirected to the <<_processor_external_memory_interface_wishbone>> (if implemented).
 |=======================

 The CPU can access all of the 32-bit address space from the instruction fetch interface and also from the data access
@ -503,14 +503,14 @@ customizable memory map implemented via VHDL constants in the main package file
 [source,vhdl]
 ----
  -- Main Address Regions ---
-  constant mem_ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
-  constant mem_dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
-  constant mem_xip_base_c    : std_ulogic_vector(31 downto 0) := x"e0000000";
-  constant mem_xip_size_c    : natural := 256*1024*1024;
-  constant mem_boot_base_c   : std_ulogic_vector(31 downto 0) := x"ffffc000";
-  constant mem_boot_size_c   : natural := 8*1024;
-  constant mem_io_base_c     : std_ulogic_vector(31 downto 0) := x"ffffe000";
-  constant mem_io_size_c     : natural := 8*1024;
+  constant mem_imem_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- IMEM size via generic
+  constant mem_dmem_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- DMEM size via generic
+  constant mem_xip_base_c  : std_ulogic_vector(31 downto 0) := x"e0000000";
+  constant mem_xip_size_c  : natural := 256*1024*1024;
+  constant mem_boot_base_c : std_ulogic_vector(31 downto 0) := x"ffffc000";
+  constant mem_boot_size_c : natural := 8*1024;
+  constant mem_io_base_c   : std_ulogic_vector(31 downto 0) := x"ffffe000";
+  constant mem_io_size_c   : natural := 8*1024;
 ----

 Besides the delegation of bus requests the gateway also implements a bus monitor (aka "the bus keeper") that tracks all
@ -585,7 +585,8 @@ Context changes, interrupts, traps, etc. do not effect nor invalidate the reserv
 The controller supports only a single global reservation set. By default this reservation set "monitors" a word-aligned
 4-byte granule. However, the granularity can be customized via the `AMO_RVS_GRANULARITY` top entity generic (see
 <<_processor_top_entity_generics>>) to cover an arbitrarily large naturally aligned address region. The only constraint is
-that the size of the address region has to be a power of two.
+that the size of the address region has to be a power of two. The configured granularity can be determined by software via
+the <<_system_configuration_information_memory_sysinfo>> module.

 .Physical Memory Attributes
 [NOTE]
--- a/docs/datasheet/soc_bootrom.adoc
+++ b/docs/datasheet/soc_bootrom.adoc
@ -17,12 +17,12 @@ This boot ROM module provides a read-only memory that contain the executable ima
 is automatically set to the beginning of the bootloader ROM. See sections <<_address_space>> and
 <<_boot_configuration>> for more information regarding the processor's different boot scenarios.

+.Memory Size
+[IMPORTANT]
+If the configured boot ROM size is **not** a power of two the actual memory size will be auto-adjusted to
+the next power of two (e.g. configuring a memory size of 6kB will result in a physical memory size of 8kB).
+
 .Bootloader Image
 [IMPORTANT]
 The boot ROM is initialized during synthesis with the default bootloader image
 (`rtl/core/neorv32_bootloader_image.vhd`).
-
-
-.Read-Only Access
-[NOTE]
-Any write access to the BOOTROM will raise a _store access fault_ exception.
--- a/docs/datasheet/soc_dmem.adoc
+++ b/docs/datasheet/soc_dmem.adoc
@ -16,9 +16,8 @@

 Implementation of the processor-internal data memory is enabled via the processor's `MEM_INT_DMEM_EN`
 generic. The size in bytes is defined via the `MEM_INT_DMEM_SIZE` generic. If the DMEM is implemented,
-the memory is mapped into the data memory space and located right at the beginning of the data memory
-space (default `dspace_base_c` = 0x80000000), see <<_address_space>>. The DMEM is always implemented
-as true RAM.
+it is mapped to base address `0x80000000` by default (see section <<_address_space>>).
+The DMEM is always implemented as true RAM.

 .Memory Size
 [IMPORTANT]
--- a/docs/datasheet/soc_imem.adoc
+++ b/docs/datasheet/soc_imem.adoc
@ -17,8 +17,7 @@

 Implementation of the processor-internal instruction memory is enabled via the processor's
 `MEM_INT_IMEM_EN` generic. The size in bytes is defined via the `MEM_INT_IMEM_SIZE` generic. If the
-IMEM is implemented, the memory is mapped into the instruction memory space and located right at the
-beginning of the instruction memory space (default `ispace_base_c` = 0x00000000), see <<_address_space>>.
+IMEM is implemented, it is mapped to base address `0x00000000` by default (see section <<_address_space>>).

 By default the IMEM is implemented as true RAM so the content can be modified during run time. This is
 required when using a bootloader that can update the content of the IMEM at any time. If you do not need
--- a/docs/datasheet/soc_sysinfo.adoc
+++ b/docs/datasheet/soc_sysinfo.adoc
@ -6,7 +6,7 @@
 [frame="topbot",grid="none"]
 |=======================
 | Hardware source file(s): | neorv32_sysinfo.vhd | 
-| Software driver file(s): | neorv32.h |
+| Software driver file(s): | neorv32_sysinfo.h |
 | Top entity port:         | none | 
 | Configuration generics:  | * | most of the top's configuration generics
 | CPU interrupts:          | none | 
@ -25,25 +25,38 @@ and default clock speed) for correct operation.
 **Register Map**

 .SYSINFO register map (`struct NEORV32_SYSINFO`)
-[cols="<2,<2,<6"]
+[cols="<2,<1,<7"]
 [options="header",grid="all"]
 |=======================
 | Address | Name [C] | Function
-| `0xfffffe00` | `CLK`         | clock speed in Hz (via top's `CLOCK_FREQUENCY` generic)
-| `0xfffffe04` | -             | _reserved_, read as zero
-| `0xfffffe08` | `SOC`         | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
-| `0xfffffe0c` | `CACHE`       | cache configuration information (see <<_sysinfo_cache_configuration>>)
-| `0xfffffe10` | `ISPACE_BASE` | instruction address space base (via package's `mem_ispace_base_c` constant)
-| `0xfffffe14` | `DSPACE_BASE` | data address space base (via package's `mem_dspace_base_c` constant)
-| `0xfffffe18` | `IMEM_SIZE`   | internal IMEM size in bytes (via top's `MEM_INT_IMEM_SIZE` generic)
-| `0xfffffe1c` | `DMEM_SIZE`   | internal DMEM size in bytes (via top's `MEM_INT_DMEM_SIZE` generic)
+| `0xfffffe00` | `CLK`    | clock speed in Hz (via top's `CLOCK_FREQUENCY` generic)
+| `0xfffffe04` | `MEM[4]` | internal memory configuration (see <<_sysinfo_memory_configuration>>)
+| `0xfffffe08` | `SOC`    | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
+| `0xfffffe0c` | `CACHE`  | cache configuration information (see <<_sysinfo_cache_configuration>>)
+|=======================
+
+
+===== SYSINFO - Memory Configuration
+
+[NOTE]
+Bit fields in this register are set to all-zero if the according cache is not implemented.
+
+.SYSINFO `MEM` Bytes
+[cols="^1,<2,<7"]
+[options="header",grid="all"]
+|=======================
+| Byte | Name [C] | Function
+| `0`  | `SYSINFO_MEM_IMEM` | _log2_(internal IMEM size in bytes), via top's `MEM_INT_IMEM_SIZE` generic
+| `1`  | `SYSINFO_MEM_DMEM` | _log2_(internal DMEM size in bytes), via top's `MEM_INT_DMEM_SIZE` generic
+| `2`  | -                  | _reserved_, read as zero
+| `3`  | `SYSINFO_MEM_RVSG` | _log2_(reservation set size granularity in bytes), via top's `AMO_RVS_GRANULARITY` generic
 |=======================


 ===== SYSINFO - SoC Configuration

-._SYSINFO_SOC_ bits
-[cols="^1,<10,<11"]
+.SYSINFO `SOC` Bits
+[cols="^2,<6,<10"]
 [options="header",grid="all"]
 |=======================
 | Bit | Name [C] | Function
@ -83,8 +96,8 @@ and default clock speed) for correct operation.
 [NOTE]
 Bit fields in this register are set to all-zero if the according cache is not implemented.

-._SYSINFO_CACHE_ bits
-[cols="^1,<10,<11"]
+.SYSINFO `CACHE` Bits
+[cols="^1,<10,<10"]
 [options="header",grid="all"]
 |=======================
 | Bit     | Name [C] | Function
--- a/docs/datasheet/software.adoc
+++ b/docs/datasheet/software.adoc
@ -322,8 +322,8 @@ __neorv32_rom_size = DEFINED(__neorv32_rom_size) ? __neorv32_rom_size : 2048M;
 __neorv32_ram_size = DEFINED(__neorv32_ram_size) ? __neorv32_ram_size : 8K;

 /* Default section base addresses */
-__neorv32_rom_base = DEFINED(__neorv32_rom_base) ? __neorv32_rom_base : 0x00000000; /* = VHDL package's "ispace_base_c" */
-__neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x80000000; /* = VHDL package's "dspace_base_c" */
+__neorv32_rom_base = DEFINED(__neorv32_rom_base) ? __neorv32_rom_base : 0x00000000;
+__neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x80000000;
 ----

 The region size and base address configuration can be edited by the user - either by explicitly
@ -336,9 +336,8 @@ $ make USER_FLAGS+="-Wl,--defsym,__neorv32_rom_size=4096" clean_all exe
 ----

 [IMPORTANT]
-`neorv32_rom_base` (= `ORIGIN` of the `ram` section) has to be always identical to the processor's `dspace_base_c` hardware
-configuration. Also, `neorv32_ram_base` (= `ORIGIN` of the `rom` section) has to be always identical to the processor's
-`ispace_base_c` hardware configuration.
+`__neorv32_rom_base` (= `ORIGIN` of the `ram` section) and `__neorv32_ram_base` (= `ORIGIN` of the `rom` section) have to
+be sync to the actual memory layout configuration of the processor (see section <<_address_space>>).

 [NOTE]
 The default configuration for the `rom` section assumes a maximum of 2GB _logical_ memory address space. This size does not
--- a/docs/datasheet/software_bootloader.adoc
+++ b/docs/datasheet/software_bootloader.adoc
@ -92,8 +92,8 @@ CLK:  0x05f5e100
 MISA: 0x40901106
 XISA: 0xc0000fab
 SOC:  0xffff402f
-IMEM: 0x00008000 bytes @0x00000000
-DMEM: 0x00002000 bytes @0x80000000
+IMEM: 0x00008000
+DMEM: 0x00002000

 Autoboot in 8s. Press any key to abort.
 ----
@ -105,12 +105,12 @@ The start-up screen gives some brief information about the bootloader and severa
 |=======================
 | `BLDV` | Bootloader version (built date).
 | `HWV`  | Processor hardware version (the <<_mimpid>> CSR); in BCD format; example: `0x01040606` = v1.4.6.6).
-| `CLK`  | Processor clock speed in Hz (via the `CLK` register from <<_system_configuration_information_memory_sysinfo>>.
+| `CLK`  | Processor clock speed in Hz (via the `CLK` register from the <<_system_configuration_information_memory_sysinfo>>.
 | `MISA` | RISC-V CPU extensions (<<_misa>> CSR).
 | `XISA` | NEORV32-specific CPU extensions (<<_mxisa>> CSR).
 | `SOC`  | Processor configuration (via the `SOC` register from the <<_system_configuration_information_memory_sysinfo>>.
-| `IMEM` | IMEM memory base address and size in byte (via the `IMEM_SIZE` and `ISPACE_BASE` registers from the <<_system_configuration_information_memory_sysinfo>>.
-| `DMEM` | DMEM memory base address and size in byte (via the `DMEM_SIZE` and `DSPACE_BASE` registers from the <<_system_configuration_information_memory_sysinfo>>.
+| `IMEM` | Internal IMEM size in byte (via the `MEM` register from the <<_system_configuration_information_memory_sysinfo>>.
+| `DMEM` | Internal DMEM size in byte (via the `MEM` register from the <<_system_configuration_information_memory_sysinfo>>.
 |=======================

 Now you have 8 seconds to press _any_ key. Otherwise, the bootloader starts the <<_auto_boot_sequence>>. When
@ -126,8 +126,8 @@ CLK:  0x05f5e100
 MISA: 0x40901106
 XISA: 0xc0000fab
 SOC:  0xffff402f
-IMEM: 0x00008000 bytes @0x00000000
-DMEM: 0x00002000 bytes @0x80000000
+IMEM: 0x00008000
+DMEM: 0x00002000

 Autoboot in 8s. Press any key to abort. <1>
 Aborted.
--- a/docs/figures/address_space.png
+++ b/docs/figures/address_space.png
--- a/docs/userguide/customizing_the_bootloader.adoc
+++ b/docs/userguide/customizing_the_bootloader.adoc
@ -19,6 +19,8 @@ minimal base + privileged ISA `rv32i_zicsr` only to ensure it can work independe
 [options="header", grid="rows"]
 |=======================
 | Parameter | Default | Legal values | Description
+4+^| Memory layout
+| `EXE_BASE_ADDR` | `0x00000000` | _any_ | Base address / boot address for the executable (see section <<_address_space>>)
 4+^| Serial console interface
 | `UART_EN`   | `1` | `0`, `1` | Set to `0` to disable UART0 (no serial console at all)
 | `UART_BAUD` | `19200` | _any_ | Baud rate of UART0
--- a/rtl/core/mem/neorv32_dmem.default.vhd
+++ b/rtl/core/mem/neorv32_dmem.default.vhd
@ -65,14 +65,11 @@ begin

  -- Sanity Checks --------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
-  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic DMEM." severity note;
-
  assert not (is_power_of_two_f(DMEM_SIZE) = false) report
    "NEORV32 PROCESSOR CONFIG ERROR: Internal DMEM size has to be a power of two!" severity error;

  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) &
+    "NEORV32 PROCESSOR CONFIG NOTE: Implementing DEFAULT processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) &
    " bytes)." severity note;


--- a/rtl/core/mem/neorv32_dmem.legacy.vhd
+++ b/rtl/core/mem/neorv32_dmem.legacy.vhd
@ -66,14 +66,11 @@ begin

  -- Sanity Checks --------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
-  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: Using legacy HDL style DMEM." severity note;
-
  assert not (is_power_of_two_f(DMEM_SIZE) = false) report
    "NEORV32 PROCESSOR CONFIG ERROR: Internal DMEM size has to be a power of two!" severity error;

  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) &
+    "NEORV32 PROCESSOR CONFIG NOTE: Implementing LEGACY processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) &
    " bytes)." severity note;


--- a/rtl/core/mem/neorv32_imem.default.vhd
+++ b/rtl/core/mem/neorv32_imem.default.vhd
@ -82,14 +82,11 @@ begin

  -- Sanity Checks --------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
-  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic IMEM." severity note;
-
  assert not (is_power_of_two_f(IMEM_SIZE) = false) report
    "NEORV32 PROCESSOR CONFIG ERROR: Internal IMEM size has to be a power of two!" severity error;

  assert not (IMEM_AS_IROM = true) report
-    "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) &
+    "NEORV32 PROCESSOR CONFIG NOTE: Implementing DEFAULT processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) &
    " bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note;

  assert not (IMEM_AS_IROM = false) report
--- a/rtl/core/mem/neorv32_imem.legacy.vhd
+++ b/rtl/core/mem/neorv32_imem.legacy.vhd
@ -83,14 +83,11 @@ begin

  -- Sanity Checks --------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
-  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: Using legacy HDL style IMEM." severity note;
-
  assert not (is_power_of_two_f(IMEM_SIZE) = false) report
    "NEORV32 PROCESSOR CONFIG ERROR: Internal IMEM size has to be a power of two!" severity error;

  assert not (IMEM_AS_IROM = true) report
-    "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) &
+    "NEORV32 PROCESSOR CONFIG NOTE: Implementing LEGACY processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) &
    " bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note;

  assert not (IMEM_AS_IROM = false) report
--- a/rtl/core/neorv32_bootloader_image.vhd
+++ b/rtl/core/neorv32_bootloader_image.vhd
@ -1,8 +1,8 @@
 -- The NEORV32 RISC-V Processor: https://github.com/stnolting/neorv32
 -- Auto-generated memory initialization file (for BOOTLOADER) from source file <bootloader/main.bin>
-- Size: 4056 bytes
+-- Size: 4012 bytes
 -- MARCH: default
-- Built: 27.07.2023 09:57:13
+-- Built: 28.07.2023 09:12:06

 -- prototype defined in 'neorv32_package.vhd'
 package body neorv32_bootloader_image is
@ -40,7 +40,7 @@ x"00000e93",
 x"00000f13",
 x"00000f93",
 x"00001597",
-x"f5c58593",
+x"f3058593",
 x"80004617",
 x"f7c60613",
 x"80004697",
@ -85,26 +85,26 @@ x"00012403",
 x"00412483",
 x"00810113",
 x"30200073",
-x"fb010113",
-x"04912223",
+x"fc010113",
+x"02912a23",
 x"800004b7",
 x"0004a223",
 x"800007b7",
 x"0007a023",
 x"ffffd7b7",
-x"04112623",
-x"04812423",
-x"05212023",
-x"03312e23",
-x"03412c23",
-x"03512a23",
-x"03612823",
-x"03712623",
-x"03812423",
-x"03912223",
-x"03a12023",
-x"01b12e23",
-x"a5478793",
+x"02112e23",
+x"02812c23",
+x"03212823",
+x"03312623",
+x"03412423",
+x"03512223",
+x"03612023",
+x"01712e23",
+x"01812c23",
+x"01912a23",
+x"01a12823",
+x"01b12623",
+x"a3478793",
 x"30579073",
 x"e0802783",
 x"00040737",
@ -162,10 +162,10 @@ x"ffff7637",
 x"00000793",
 x"5ff70713",
 x"a0060613",
-x"1ed76c63",
+x"1ed76463",
 x"00000713",
 x"3fe00613",
-x"1ef66c63",
+x"1ef66463",
 x"000106b7",
 x"fff78793",
 x"00679793",
@ -192,60 +192,56 @@ x"30479073",
 x"00800793",
 x"3007a073",
 x"ffffd537",
-x"dec50513",
-x"6bc000ef",
+x"dbc50513",
+x"69c000ef",
 x"f1302573",
-x"640000ef",
+x"620000ef",
 x"ffffd537",
-x"e2450513",
-x"6a8000ef",
+x"df450513",
+x"688000ef",
 x"e0002503",
-x"62c000ef",
-x"ffffd537",
-x"e2c50513",
-x"694000ef",
-x"30102573",
-x"618000ef",
-x"ffffd537",
-x"e3450513",
-x"680000ef",
-x"fc002573",
-x"604000ef",
-x"ffffd537",
-x"e3c50513",
-x"66c000ef",
-x"e0802503",
-x"ffffd437",
-x"ffffd937",
-x"5e8000ef",
-x"ffffd537",
-x"e4450513",
-x"650000ef",
-x"e1802503",
-x"5d4000ef",
-x"e4c40513",
-x"640000ef",
-x"e1002503",
-x"5c4000ef",
-x"ffffd537",
-x"e5850513",
-x"62c000ef",
-x"e1c02503",
-x"5b0000ef",
-x"e4c40513",
-x"61c000ef",
-x"e1402503",
-x"5a0000ef",
-x"de890513",
 x"60c000ef",
+x"ffffd537",
+x"dfc50513",
+x"674000ef",
+x"30102573",
+x"5f8000ef",
+x"ffffd537",
+x"e0450513",
+x"660000ef",
+x"fc002573",
+x"5e4000ef",
+x"ffffd537",
+x"e0c50513",
+x"64c000ef",
+x"e0802503",
+x"00100413",
+x"ffffd937",
+x"5c8000ef",
+x"ffffd537",
+x"e1450513",
+x"630000ef",
+x"e0404503",
+x"00a41533",
+x"ffc57513",
+x"5ac000ef",
+x"ffffd537",
+x"e1c50513",
+x"614000ef",
+x"e0504783",
+x"00f41533",
+x"ffc57513",
+x"590000ef",
+x"db890513",
+x"5fc000ef",
 x"e0802783",
 x"00010737",
 x"00e7f7b3",
 x"04078e63",
 x"ffffd537",
-x"e6050513",
-x"5f0000ef",
-x"2c8000ef",
+x"e2450513",
+x"5e0000ef",
+x"2b8000ef",
 x"e0002403",
 x"00020ab7",
 x"fffffa37",
@ -262,18 +258,18 @@ x"0167f7b3",
 x"0a078063",
 x"ffffd537",
 x"504a2783",
-x"e8c50513",
-x"5a4000ef",
+x"e5050513",
+x"594000ef",
 x"ffffda37",
-x"e98a0513",
-x"598000ef",
+x"e5ca0513",
+x"588000ef",
 x"fffffab7",
 x"06c00b13",
 x"07800c13",
 x"07300c93",
 x"ffffd7b7",
-x"f1878513",
-x"57c000ef",
+x"edc78513",
+x"56c000ef",
 x"500aa783",
 x"000106b7",
 x"00d7f7b3",
@ -281,72 +277,72 @@ x"fe078ae3",
 x"504aa403",
 x"0ff47413",
 x"00040513",
-x"4cc000ef",
-x"de890513",
-x"554000ef",
+x"4bc000ef",
+x"db890513",
+x"544000ef",
 x"07200793",
 x"06f41063",
 x"ffffc2b7",
 x"00028067",
 x"00c686b3",
 x"00178793",
-x"e01ff06f",
+x"e11ff06f",
 x"ffe70693",
 x"ffd6f693",
 x"00069863",
 x"0037d793",
 x"00170713",
-x"df5ff06f",
+x"e05ff06f",
 x"0017d793",
 x"ff5ff06f",
-x"1f0000ef",
+x"1e0000ef",
 x"f485e4e3",
 x"00b41463",
 x"f53560e3",
 x"00100513",
-x"738000ef",
-x"de890513",
-x"4f8000ef",
+x"728000ef",
+x"db890513",
+x"4e8000ef",
 x"00000513",
-x"089000ef",
-x"19640c63",
+x"069000ef",
+x"19640463",
 x"028b6663",
 x"06500793",
-x"18f40a63",
+x"18f40263",
 x"06800793",
-x"e98a0513",
+x"e5ca0513",
 x"02f40c63",
 x"03f00793",
-x"18f40e63",
+x"18f40663",
 x"ffffd537",
-x"fa850513",
+x"f7c50513",
 x"0240006f",
 x"07500793",
 x"02f40263",
-x"17840e63",
+x"17840663",
 x"ff9414e3",
 x"0044a403",
 x"02041063",
 x"ffffd537",
-x"f2050513",
-x"49c000ef",
+x"ee450513",
+x"48c000ef",
 x"f15ff06f",
 x"00000513",
-x"6c8000ef",
+x"6b8000ef",
 x"f09ff06f",
 x"ffffd537",
-x"f3c50513",
-x"480000ef",
+x"f0050513",
+x"470000ef",
 x"00040513",
-x"404000ef",
+x"3f4000ef",
 x"ffffd537",
-x"f4450513",
-x"46c000ef",
+x"f0850513",
+x"45c000ef",
 x"00400537",
-x"3f0000ef",
+x"3e0000ef",
 x"ffffd537",
-x"f5c50513",
-x"458000ef",
+x"f2050513",
+x"448000ef",
 x"fffff737",
 x"00010637",
 x"50072783",
@ -355,49 +351,45 @@ x"fe078ce3",
 x"50472983",
 x"0ff9f993",
 x"00098513",
-x"3a4000ef",
+x"394000ef",
 x"07900793",
 x"eaf994e3",
-x"2b0000ef",
+x"2a0000ef",
 x"00050663",
 x"00300513",
-x"474000ef",
+x"464000ef",
 x"ffffd537",
-x"f6850513",
-x"410000ef",
+x"f2c50513",
+x"400000ef",
 x"01045b93",
 x"004009b7",
 x"00010db7",
 x"fff00d13",
-x"230000ef",
-x"154000ef",
+x"220000ef",
+x"144000ef",
 x"0d800513",
-x"0f8000ef",
+x"0e8000ef",
 x"00098513",
-x"108000ef",
-x"0d8000ef",
-x"234000ef",
+x"0f8000ef",
+x"0c8000ef",
+x"224000ef",
 x"00157513",
 x"fe051ce3",
 x"fffb8b93",
 x"01b989b3",
 x"fdab98e3",
-x"e1002683",
 x"004009b7",
 x"00000d13",
 x"00000d93",
 x"00c98793",
-x"00dd0733",
-x"00072583",
+x"000d2583",
 x"00fd0533",
-x"00d12623",
-x"00bd8db3",
-x"27c000ef",
-x"004007b7",
 x"004d0d13",
-x"00c12683",
+x"00bd8db3",
+x"274000ef",
+x"004007b7",
 x"00c78793",
-x"fc8d6ce3",
+x"fe8d62e3",
 x"4788d5b7",
 x"afe58593",
 x"00400537",
@ -409,20 +401,20 @@ x"00898513",
 x"41b005b3",
 x"240000ef",
 x"ffffd537",
-x"dd050513",
-x"ebdff06f",
+x"da050513",
+x"ecdff06f",
 x"00100513",
-x"ec1ff06f",
+x"ed1ff06f",
 x"0044a783",
-x"e4079ae3",
+x"e60792e3",
 x"ffffd537",
-x"f7850513",
-x"ea1ff06f",
+x"f3c50513",
+x"eb1ff06f",
 x"00100513",
-x"e45ff06f",
+x"e55ff06f",
 x"ffffd537",
-x"f8850513",
-x"e8dff06f",
+x"f4c50513",
+x"e9dff06f",
 x"fffff737",
 x"40472583",
 x"40072503",
@ -608,7 +600,7 @@ x"07800513",
 x"ffffd4b7",
 x"fb9ff0ef",
 x"01c00413",
-x"fb448493",
+x"f8848493",
 x"ffc00993",
 x"008957b3",
 x"00f7f793",
@ -650,13 +642,13 @@ x"ff010113",
 x"00812423",
 x"00050413",
 x"ffffd537",
-x"d8850513",
+x"d5850513",
 x"00112623",
 x"f91ff0ef",
 x"00241793",
 x"ffffd537",
 x"008787b3",
-x"fc450513",
+x"f9850513",
 x"00f50533",
 x"f79ff0ef",
 x"00800793",
@ -748,7 +740,7 @@ x"00020737",
 x"00e7f7b3",
 x"04078263",
 x"ffffd537",
-x"d9050513",
+x"d6050513",
 x"e0dff0ef",
 x"00048513",
 x"d91ff0ef",
@ -761,7 +753,7 @@ x"d5dff0ef",
 x"34302573",
 x"d71ff0ef",
 x"ffffd537",
-x"de850513",
+x"db850513",
 x"dd9ff0ef",
 x"00440413",
 x"34141073",
@ -778,60 +770,58 @@ x"01312e23",
 x"01412c23",
 x"01512a23",
 x"01712623",
-x"01812423",
 x"00fb2023",
 x"00050413",
 x"02051863",
 x"ffffd537",
-x"d9c50513",
-x"d81ff0ef",
+x"d6c50513",
+x"d85ff0ef",
 x"004005b7",
 x"00040513",
-x"ae9ff0ef",
+x"aedff0ef",
 x"4788d7b7",
 x"afe78793",
 x"04f50863",
 x"00000513",
 x"0380006f",
 x"ffffd537",
-x"dbc50513",
-x"d55ff0ef",
+x"d8c50513",
+x"d59ff0ef",
 x"00400537",
-x"cd9ff0ef",
+x"cddff0ef",
 x"ffffd537",
-x"dc850513",
-x"d41ff0ef",
+x"d9850513",
+x"d45ff0ef",
 x"e0802783",
 x"00040737",
 x"00e7f7b3",
 x"00079663",
 x"00300513",
-x"d81ff0ef",
-x"badff0ef",
+x"d85ff0ef",
+x"bb1ff0ef",
 x"fa0502e3",
 x"ff1ff06f",
 x"004009b7",
 x"00498593",
 x"00040513",
-x"a81ff0ef",
+x"a85ff0ef",
 x"00050a13",
 x"00898593",
 x"00040513",
-x"a71ff0ef",
-x"e1002c03",
+x"a75ff0ef",
 x"00050a93",
 x"ffca7b93",
 x"00000913",
 x"00000493",
 x"00c98993",
 x"013905b3",
-x"05791c63",
+x"05791a63",
 x"015484b3",
 x"00200513",
-x"fa0494e3",
+x"fa0496e3",
 x"ffffd537",
-x"dd050513",
-x"cc5ff0ef",
+x"da050513",
+x"ccdff0ef",
 x"02c12083",
 x"02812403",
 x"800007b7",
@ -844,32 +834,30 @@ x"01812a03",
 x"01412a83",
 x"01012b03",
 x"00c12b83",
-x"00812c03",
 x"03010113",
 x"00008067",
 x"00040513",
-x"9f5ff0ef",
-x"012c07b3",
+x"a01ff0ef",
+x"00a92023",
 x"00a484b3",
-x"00a7a023",
 x"00490913",
-x"f8dff06f",
+x"f95ff06f",
 x"ff010113",
 x"00112623",
 x"00812423",
 x"00800793",
 x"3007b073",
-x"e1002403",
+x"00000413",
 x"00050463",
 x"e0400437",
 x"ffffd537",
-x"dd450513",
-x"c41ff0ef",
+x"da450513",
+x"c51ff0ef",
 x"00040513",
-x"bc5ff0ef",
+x"bd5ff0ef",
 x"ffffd537",
-x"de450513",
-x"c2dff0ef",
+x"db450513",
+x"c3dff0ef",
 x"fffff737",
 x"50072783",
 x"fe07cee3",
@ -909,7 +897,7 @@ x"0a3e3e20",
 x"444c420a",
 x"4a203a56",
 x"32206c75",
-x"30322037",
+x"30322038",
 x"480a3332",
 x"203a5657",
 x"00000020",
@ -923,9 +911,6 @@ x"434f530a",
 x"0020203a",
 x"454d490a",
 x"00203a4d",
-x"74796220",
-x"40207365",
-x"00000000",
 x"454d440a",
 x"00203a4d",
 x"7475410a",
@ -1002,14 +987,18 @@ x"65206f4e",
 x"75636578",
 x"6c626174",
 x"00002e65",
-x"68746967",
-x"632e6275",
-x"732f6d6f",
-x"6c6f6e74",
-x"676e6974",
-x"6f656e2f",
-x"32337672",
-x"00000000",
+x"53207962",
+x"68706574",
+x"4e206e61",
+x"69746c6f",
+x"670a676e",
+x"75687469",
+x"6f632e62",
+x"74732f6d",
+x"746c6f6e",
+x"2f676e69",
+x"726f656e",
+x"00323376",
 x"61766e49",
 x"2064696c",
 x"00444d43",
--- a/rtl/core/neorv32_cpu.vhd
+++ b/rtl/core/neorv32_cpu.vhd
@ -147,7 +147,7 @@ begin

  -- CPU ISA configuration --
  assert false report
-    "NEORV32 CPU CONFIG NOTE: Core ISA ('MARCH') = RV32" &
+    "NEORV32 CPU Configuration: RV32" &
    cond_sel_string_f(CPU_EXTENSION_RISCV_E,        "E", "I") &
    cond_sel_string_f(CPU_EXTENSION_RISCV_M,        "M", "") &
    cond_sel_string_f(CPU_EXTENSION_RISCV_A,        "A", "") &
@ -170,14 +170,10 @@ begin
  -- simulation notifier --
  assert not (is_simulation_c = true) report
    "NEORV32 CPU WARNING! Assuming this is a simulation." severity warning;
-  assert not (is_simulation_c = false) report
-    "NEORV32 CPU NOTE: Assuming this is real hardware." severity note;

  -- CPU boot address --
  assert not (CPU_BOOT_ADDR(1 downto 0) /= "00") report
    "NEORV32 CPU CONFIG ERROR! <CPU_BOOT_ADDR> has to be 32-bit aligned." severity error;
-  assert false report
-    "NEORV32 CPU CONFIG NOTE: Boot from address 0x" & to_hstring32_f(CPU_BOOT_ADDR) & "." severity note;

  -- Instruction prefetch buffer --
  assert not (is_power_of_two_f(CPU_IPB_ENTRIES) = false) report
--- a/rtl/core/neorv32_dcache.vhd
+++ b/rtl/core/neorv32_dcache.vhd
@ -133,8 +133,6 @@ begin
    "NEORV32 PROCESSOR CONFIG ERROR! d-cache number of blocks <DCACHE_NUM_BLOCKS> has to be >= 1." severity error;
  assert not (DCACHE_BLOCK_SIZE < 4) report
    "NEORV32 PROCESSOR CONFIG ERROR! d-cache block size <DCACHE_BLOCK_SIZE> has to be >= 4." severity error;
-  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: d-cache uncached memory space 0x" & to_hstring32_f(DCACHE_UC_PBEGIN & x"0000000") & "..0xffffffff." severity note;


  -- Control Engine FSM Sync ----------------------------------------------------------------
--- a/rtl/core/neorv32_icache.vhd
+++ b/rtl/core/neorv32_icache.vhd
@ -136,8 +136,6 @@ begin
    "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size <ICACHE_BLOCK_SIZE> has to be >= 4." severity error;
  assert not ((ICACHE_NUM_SETS = 0) or (ICACHE_NUM_SETS > 2)) report
    "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be 1 (direct-mapped) or 2 (2-way set-associative)." severity error;
-  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: i-cache uncached memory space 0x" & to_hstring32_f(ICACHE_UC_PBEGIN & x"0000000") & "..0xffffffff." severity note;


  -- Control Engine FSM Sync ----------------------------------------------------------------
--- a/rtl/core/neorv32_intercon.vhd
+++ b/rtl/core/neorv32_intercon.vhd
@ -362,12 +362,6 @@ architecture neorv32_gateway_rtl of neorv32_gateway is

 begin

-  -- Sanity Checks --------------------------------------------------------------------------
-  -- -------------------------------------------------------------------------------------------
-  assert false report
-    "NEORV32 PROCESSOR CONFIG NOTE: Processor-internal bus timeout after " & integer'image(TIMEOUT) & " cycles." severity note;
-
-
  -- Address Section Decoder ----------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  port_sel(port_imem_c) <= '1' when (main_req_i.addr(31 downto index_size_f(IMEM_SIZE)) = IMEM_BASE(31 downto index_size_f(IMEM_SIZE))) and (IMEM_ENABLE = true) else '0';
@ -381,7 +375,8 @@ begin
                                   (port_sel(port_dmem_c) = '0') and
                                   (port_sel(port_xip_c)  = '0') and
                                   (port_sel(port_boot_c) = '0') and
-                                   (port_sel(port_io_c)   = '0') and (EXT_ENABLE = true) else '0';
+                                   (port_sel(port_io_c)   = '0') and
+                                   (EXT_ENABLE = true) else '0';


  -- Bus Request (also enforce PMAs here) ---------------------------------------------------
--- a/rtl/core/neorv32_package.vhd
+++ b/rtl/core/neorv32_package.vhd
@ -56,7 +56,7 @@ package neorv32_package is

  -- Architecture Constants -----------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080702"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080703"; -- hardware version
  constant archid_c     : natural := 19; -- official RISC-V architecture ID
  constant XLEN         : natural := 32; -- native data path width, do not change!

@ -79,14 +79,14 @@ package neorv32_package is
 -- ****************************************************************************************************************************

  -- Main Address Regions ---
-  constant mem_ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- IMEM size via generic
-  constant mem_dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- DMEM size via generic
-  constant mem_xip_base_c    : std_ulogic_vector(31 downto 0) := x"e0000000"; -- page (4MSBs) only!
-  constant mem_xip_size_c    : natural := 256*1024*1024;
-  constant mem_boot_base_c   : std_ulogic_vector(31 downto 0) := x"ffffc000";
-  constant mem_boot_size_c   : natural := 8*1024;
-  constant mem_io_base_c     : std_ulogic_vector(31 downto 0) := x"ffffe000";
-  constant mem_io_size_c     : natural := 8*1024;
+  constant mem_imem_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- IMEM size via generic
+  constant mem_dmem_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- DMEM size via generic
+  constant mem_xip_base_c  : std_ulogic_vector(31 downto 0) := x"e0000000"; -- page (4MSBs) only!
+  constant mem_xip_size_c  : natural := 256*1024*1024;
+  constant mem_boot_base_c : std_ulogic_vector(31 downto 0) := x"ffffc000";
+  constant mem_boot_size_c : natural := 8*1024;
+  constant mem_io_base_c   : std_ulogic_vector(31 downto 0) := x"ffffe000";
+  constant mem_io_size_c   : natural := 8*1024;

  -- Start of uncached memory access (page / 4MSBs only) --
  constant uncached_begin_c  : std_ulogic_vector(31 downto 0) := x"f0000000";
--- a/rtl/core/neorv32_sysinfo.vhd
+++ b/rtl/core/neorv32_sysinfo.vhd
@ -55,6 +55,8 @@ entity neorv32_sysinfo is
    -- Internal data memory --
    MEM_INT_DMEM_EN      : boolean; -- implement processor-internal data memory
    MEM_INT_DMEM_SIZE    : natural; -- size of processor-internal data memory in bytes
+    -- Reservation Set Granularity --
+    AMO_RVS_GRANULARITY  : natural; -- size in bytes, has to be a power of 2, min 4
    -- Instruction cache --
    ICACHE_EN            : boolean; -- implement instruction cache
    ICACHE_NUM_BLOCKS    : natural; -- i-cache: number of blocks (min 2), has to be a power of 2
@ -104,18 +106,21 @@ architecture neorv32_sysinfo_rtl of neorv32_sysinfo is
  constant int_dmem_en_c : boolean := MEM_INT_DMEM_EN and boolean(MEM_INT_DMEM_SIZE > 0);

  -- system information ROM --
-  type sysinfo_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
+  type sysinfo_t is array (0 to 3) of std_ulogic_vector(31 downto 0);
  signal sysinfo : sysinfo_t;

 begin

  -- Construct Info ROM ---------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
-  -- SYSINFO(0): Processor (primary) clock frequency --
+  -- SYSINFO(0): Processor Clock Frequency --
  sysinfo(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));

-  -- SYSINFO(1): reserved --
-  sysinfo(1) <= (others => '0');
+  -- SYSINFO(1): Internal Memory Configuration (sizes)
+  sysinfo(1)(07 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_IMEM_SIZE), 8)); -- log2(IMEM size)
+  sysinfo(1)(15 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_DMEM_SIZE), 8)); -- log2(DMEM size)
+  sysinfo(1)(23 downto 16) <= (others => '0'); -- reserved
+  sysinfo(1)(31 downto 24) <= std_ulogic_vector(to_unsigned(index_size_f(AMO_RVS_GRANULARITY), 8)); -- log2(reservation set granularity)

  -- SYSINFO(2): SoC Configuration --
  -- Memory System --
@ -154,7 +159,7 @@ begin
  sysinfo(2)(30) <= bool_to_ulogic_f(IO_ONEWIRE_EN);       -- 1-wire interface (ONEWIRE) implemented?
  sysinfo(2)(31) <= bool_to_ulogic_f(ON_CHIP_DEBUGGER_EN); -- on-chip debugger implemented?

-  -- SYSINFO(3): Cache configuration --
+  -- SYSINFO(3): Cache Configuration --
  sysinfo(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE),    4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
  sysinfo(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS),    4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(number_of_block)
  sysinfo(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(associativity)
@ -165,18 +170,6 @@ begin
  sysinfo(3)(27 downto 24) <= (others => '0'); -- d-cache: log2(associativity)
  sysinfo(3)(31 downto 28) <= (others => '0'); -- d-cache: replacement strategy

-  -- SYSINFO(4): Base address of instruction memory space --
-  sysinfo(4) <= mem_ispace_base_c; -- defined in neorv32_package.vhd file
-
-  -- SYSINFO(5): Base address of data memory space --
-  sysinfo(5) <= mem_dspace_base_c; -- defined in neorv32_package.vhd file
-
-  -- SYSINFO(6): Size of internal IMEM in bytes --
-  sysinfo(6) <= std_ulogic_vector(to_unsigned(MEM_INT_IMEM_SIZE, 32)) when (MEM_INT_IMEM_EN = true) else (others => '0');
-
-  -- SYSINFO(7): Size of internal DMEM in bytes --
-  sysinfo(7) <= std_ulogic_vector(to_unsigned(MEM_INT_DMEM_SIZE, 32)) when (MEM_INT_DMEM_EN = true) else (others => '0');
-

  -- Read Access ----------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
@ -186,7 +179,7 @@ begin
      bus_rsp_o.ack  <= bus_req_i.re; -- read-only!
      bus_rsp_o.data <= (others => '0');
      if (bus_req_i.re = '1') then
-        bus_rsp_o.data <= sysinfo(to_integer(unsigned(bus_req_i.addr(4 downto 2))));
+        bus_rsp_o.data <= sysinfo(to_integer(unsigned(bus_req_i.addr(3 downto 2))));
      end if;
    end if;
  end process read_access;
--- a/rtl/core/neorv32_top.vhd
+++ b/rtl/core/neorv32_top.vhd
@ -254,7 +254,7 @@ end neorv32_top;
 architecture neorv32_top_rtl of neorv32_top is

  -- auto-configuration --
-  constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_suv_f(INT_BOOTLOADER_EN, mem_boot_base_c, mem_ispace_base_c);
+  constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_suv_f(INT_BOOTLOADER_EN, mem_boot_base_c, mem_imem_base_c);
  constant io_reg_buf_en_c : boolean := ICACHE_EN or DCACHE_EN;
  constant imem_as_rom_c   : boolean := not INT_BOOTLOADER_EN;
  constant io_gpio_en_c    : boolean := boolean(IO_GPIO_NUM > 0);
@ -351,15 +351,13 @@ begin
  if (true) generate

    assert false report
-      "NEORV32 PROCESSOR CONFIGURATION: " &
+      "NEORV32 Processor Configuration: " &
      cond_sel_string_f(MEM_INT_IMEM_EN, "IMEM ", "") &
      cond_sel_string_f(MEM_INT_DMEM_EN, "DMEM ", "") &
      cond_sel_string_f(INT_BOOTLOADER_EN, "BOOTROM ", "") &
      cond_sel_string_f(ICACHE_EN, "I-CACHE ", "") &
      cond_sel_string_f(DCACHE_EN, "D-CACHE ", "") &
      cond_sel_string_f(MEM_EXT_EN, "WISHBONE ", "") &
-      cond_sel_string_f(ON_CHIP_DEBUGGER_EN, "OCD ", "") &
-      "+ " &
      cond_sel_string_f(io_gpio_en_c, "GPIO ", "") &
      cond_sel_string_f(IO_MTIME_EN, "MTIME ", "") &
      cond_sel_string_f(IO_UART0_EN, "UART0 ", "") &
@ -379,17 +377,11 @@ begin
      cond_sel_string_f(IO_DMA_EN, "DMA ", "") &
      cond_sel_string_f(IO_SLINK_EN, "SLINK ", "") &
      cond_sel_string_f(IO_CRC_EN, "CRC ", "") &
+      cond_sel_string_f(true, "SYSINFO ", "") &
+      cond_sel_string_f(ON_CHIP_DEBUGGER_EN, "OCD ", "") &
      ""
      severity note;

-    -- boot configuration --
-    assert not (INT_BOOTLOADER_EN = true) report
-      "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM)." severity note;
-    assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = true)) report
-      "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration = direct boot from memory (processor-internal IMEM)." severity note;
-    assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = false)) report
-      "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration = direct boot from memory (processor-external memory)." severity note;
-
    -- internal memory sizes --
    assert not ((imem_size_valid_c = false) and (MEM_INT_IMEM_EN = true)) report
      "NEORV32 PROCESSOR CONFIG WARNING: Configured internal IMEM size (" & natural'image(MEM_INT_IMEM_SIZE) & " bytes) is not a power of two. " &
@ -398,13 +390,9 @@ begin
      "NEORV32 PROCESSOR CONFIG WARNING: Configured internal DMEM size (" & natural'image(MEM_INT_DMEM_SIZE) & " bytes) is not a power of two. " &
      "Auto-increasing memory size to the next power of two (" & natural'image(dmem_size_c) & " bytes)" severity warning;

-    -- on-chip debugger --
-    assert not (ON_CHIP_DEBUGGER_EN = true) report
-      "NEORV32 PROCESSOR CONFIG NOTE: Implementing on-chip debugger (OCD)." severity note;
-
    -- caches --
    assert not ((ICACHE_EN = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report
-      "NEORV32 CPU CONFIG WARNING! <CPU_EXTENSION_RISCV_Zifencei> ISA extension is required to perform i-cache memory sync operations." severity warning;
+      "NEORV32 CPU CONFIG ERROR: <CPU_EXTENSION_RISCV_Zifencei> ISA extension is required to perform i-cache memory sync. operations." severity error;

  end generate; -- /sanity_checks

@ -729,11 +717,11 @@ begin
    TIMEOUT     => max_proc_int_response_time_c,
    -- IMEM port --
    IMEM_ENABLE => MEM_INT_IMEM_EN,
-    IMEM_BASE   => mem_ispace_base_c,
+    IMEM_BASE   => mem_imem_base_c,
    IMEM_SIZE   => imem_size_c,
    -- DMEM port --
    DMEM_ENABLE => MEM_INT_DMEM_EN,
-    DMEM_BASE   => mem_dspace_base_c,
+    DMEM_BASE   => mem_dmem_base_c,
    DMEM_SIZE   => dmem_size_c,
    -- XIP port --
    XIP_ENABLE  => IO_XIP_EN,
@ -1488,6 +1476,8 @@ begin
      -- Internal Data memory --
      MEM_INT_DMEM_EN      => MEM_INT_DMEM_EN,
      MEM_INT_DMEM_SIZE    => dmem_size_c,
+      -- Reservation Set Granularity --
+      AMO_RVS_GRANULARITY  => AMO_RVS_GRANULARITY,
      -- Instruction cache --
      ICACHE_EN            => ICACHE_EN,
      ICACHE_NUM_BLOCKS    => ICACHE_NUM_BLOCKS,
--- a/rtl/core/neorv32_trng.vhd
+++ b/rtl/core/neorv32_trng.vhd
@ -130,10 +130,9 @@ begin
  -- -------------------------------------------------------------------------------------------
  assert not (IO_TRNG_FIFO < 1) report
    "NEORV32 PROCESSOR CONFIG ERROR: TRNG FIFO size <IO_TRNG_FIFO> has to be >= 1." severity error;
+
  assert not (is_power_of_two_f(IO_TRNG_FIFO) = false) report
    "NEORV32 PROCESSOR CONFIG ERROR: TRNG FIFO size <IO_TRNG_FIFO> has to be a power of two." severity error;
-  assert not (sim_mode_c = true) report
-    "NEORV32 PROCESSOR CONFIG WARNING: TRNG uses SIMULATION mode!" severity warning;


  -- Write Access ---------------------------------------------------------------------------
@ -392,7 +391,6 @@ begin
  -- Sanity Checks --------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  assert not (true) report "<< neoTRNG V2 - A Tiny and Platform-Independent True Random Number Generator for any FPGA >>" severity note;
-  assert not (POST_PROC_EN = true) report "neoTRNG note: Post-processing enabled." severity note;
  assert not (IS_SIM = true) report "neoTRNG WARNING: Simulation mode (PRNG!) enabled!" severity warning;
  assert not (NUM_CELLS < 2) report "neoTRNG config ERROR: Total number of ring-oscillator cells <NUM_CELLS> has to be >= 2." severity error;
  assert not ((NUM_INV_START mod 2)  = 0) report "neoTRNG config ERROR: Number of inverters in first cell <NUM_INV_START> has to be odd." severity error;
@ -717,7 +715,6 @@ begin
  -- For simulation/debugging only! --
  sim_rng:
  if (IS_SIM = true) generate
-    assert false report "neoTRNG WARNING: Implementing simulation-only PRNG (LFSR)!" severity warning;
    sim_lfsr: process(rstn_i, clk_i)
    begin
      if (rstn_i = '0') then
--- a/sw/bootloader/bootloader.c
+++ b/sw/bootloader/bootloader.c
@ -49,6 +49,13 @@
 **************************************************************************/
 /**@{*/

+/* -------- Memory layout -------- */
+
+/** Memory base address for the executable */
+#ifndef EXE_BASE_ADDR
+  #define EXE_BASE_ADDR 0x00000000UL
+#endif
+
 /* -------- UART interface -------- */

 /** Set to 0 to disable UART interface */
@ -324,7 +331,7 @@ int main(void) {
  // Show bootloader intro and system info
  // ------------------------------------------------
  PRINT_TEXT("\n\n\n<< NEORV32 Bootloader >>\n\n"
-                     "BLDV: "__DATE__"\nHWV:  ");
+             "BLDV: "__DATE__"\nHWV:  ");
  PRINT_XNUM(neorv32_cpu_csr_read(CSR_MIMPID));
  PRINT_TEXT("\nCLK:  ");
  PRINT_XNUM(NEORV32_SYSINFO->CLK);
@ -335,12 +342,9 @@ int main(void) {
  PRINT_TEXT("\nSOC:  ");
  PRINT_XNUM(NEORV32_SYSINFO->SOC);
  PRINT_TEXT("\nIMEM: ");
-  PRINT_XNUM(NEORV32_SYSINFO->IMEM_SIZE); PRINT_TEXT(" bytes @");
-  PRINT_XNUM(NEORV32_SYSINFO->ISPACE_BASE);
+  PRINT_XNUM((uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_IMEM]) & 0xFFFFFFFCUL);
  PRINT_TEXT("\nDMEM: ");
-  PRINT_XNUM(NEORV32_SYSINFO->DMEM_SIZE);
-  PRINT_TEXT(" bytes @");
-  PRINT_XNUM(NEORV32_SYSINFO->DSPACE_BASE);
+  PRINT_XNUM((uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_DMEM]) & 0xFFFFFFFCUL);
  PRINT_TEXT("\n");


@ -425,7 +429,7 @@ int main(void) {
    }
 #endif
    else if (c == '?') {
-      PRINT_TEXT("github.com/stnolting/neorv32");
+      PRINT_TEXT("by Stephan Nolting\ngithub.com/stnolting/neorv32");
    }
    else { // unknown command
      PRINT_TEXT("Invalid CMD");
@ -467,7 +471,7 @@ void start_app(int boot_xip) {
  // deactivate global IRQs
  neorv32_cpu_csr_clr(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE);

-  register uint32_t app_base = NEORV32_SYSINFO->ISPACE_BASE; // default = start at beginning of IMEM
+  register uint32_t app_base = (uint32_t)EXE_BASE_ADDR; // default = start at beginning of IMEM
 #if (XIP_EN != 0)
  if (boot_xip) {
    app_base = (uint32_t)(XIP_MEM_BASE_ADDRESS + SPI_BOOT_BASE_ADDR); // start from XIP mapped address
@ -576,7 +580,7 @@ void get_exe(int src) {
  uint32_t check = get_exe_word(src, addr + EXE_OFFSET_CHECKSUM); // complement sum checksum

  // transfer program data
-  uint32_t *pnt = (uint32_t*)NEORV32_SYSINFO->ISPACE_BASE;
+  uint32_t *pnt = (uint32_t*)EXE_BASE_ADDR;
  uint32_t checksum = 0;
  uint32_t d = 0, i = 0;
  addr = addr + EXE_OFFSET_DATA;
@ -646,7 +650,7 @@ void save_exe(void) {

  // store data from instruction memory and update checksum
  uint32_t checksum = 0;
-  uint32_t *pnt = (uint32_t*)NEORV32_SYSINFO->ISPACE_BASE;
+  uint32_t *pnt = (uint32_t*)EXE_BASE_ADDR;
  addr = addr + EXE_OFFSET_DATA;
  uint32_t i = 0;
  while (i < size) { // in chunks of 4 bytes
--- a/sw/common/neorv32.ld
+++ b/sw/common/neorv32.ld
@ -64,8 +64,8 @@ __neorv32_ram_size = DEFINED(__neorv32_ram_size) ? __neorv32_ram_size : 8K;
 __neorv32_heap_size = DEFINED(__neorv32_heap_size) ? __neorv32_heap_size : 0;

 /* Default section base addresses */
-__neorv32_rom_base = DEFINED(__neorv32_rom_base) ? __neorv32_rom_base : 0x00000000; /* = VHDL package's "ispace_base_c" */
-__neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x80000000; /* = VHDL package's "dspace_base_c" */
+__neorv32_rom_base = DEFINED(__neorv32_rom_base) ? __neorv32_rom_base : 0x00000000;
+__neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x80000000;


 /* ************************************************************************************************* */
--- a/sw/lib/include/neorv32_sysinfo.h
+++ b/sw/lib/include/neorv32_sysinfo.h
@ -47,49 +47,53 @@
 /**@{*/
 /** SYSINFO module prototype - whole module is read-only */
 typedef volatile struct __attribute__((packed,aligned(4))) {
-  const uint32_t CLK;         /**< offset 0:  clock speed in Hz */
-  const uint32_t reserved;    /**< offset 4:  reserved */
-  const uint32_t SOC;         /**< offset 8:  SoC features (#NEORV32_SYSINFO_SOC_enum) */
-  const uint32_t CACHE;       /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
-  const uint32_t ISPACE_BASE; /**< offset 16: instruction memory address space base */
-  const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */
-  const uint32_t IMEM_SIZE;   /**< offset 24: internal instruction memory (IMEM) size in bytes */
-  const uint32_t DMEM_SIZE;   /**< offset 28: internal data memory (DMEM) size in bytes */
+  const uint32_t CLK;    /**< offset 0:  clock speed in Hz */
+  const uint8_t  MEM[4]; /**< offset 4:  Memory configuration (sizes) (#NEORV32_SYSINFO_MEM_enum) */
+  const uint32_t SOC;    /**< offset 8:  SoC features (#NEORV32_SYSINFO_SOC_enum) */
+  const uint32_t CACHE;  /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
 } neorv32_sysinfo_t;

 /** SYSINFO module hardware access (#neorv32_sysinfo_t) */
 #define NEORV32_SYSINFO ((neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE))

+/** NEORV32_SYSINFO->MEM (r/-): Memory configuration (sizes) */
+enum NEORV32_SYSINFO_MEM_enum {
+  SYSINFO_MEM_IMEM =  0, /**< SYSINFO_MEM byte 0 (r/-): log2(internal IMEM size in bytes) (via MEM_INT_IMEM_SIZE generic) */
+  SYSINFO_MEM_DMEM =  1, /**< SYSINFO_MEM byte 1 (r/-): log2(internal DMEM size in bytes) (via MEM_INT_DMEM_SIZE generic) */
+
+  SYSINFO_MEM_RVSG =  3  /**< SYSINFO_MEM byte 3 (r/-): log2(reservation set granularity in bytes) (via AMO_RVS_GRANULARITY generic) */
+};
+
 /** NEORV32_SYSINFO->SOC (r/-): Implemented processor devices/features */
 enum NEORV32_SYSINFO_SOC_enum {
-  SYSINFO_SOC_BOOTLOADER     =  0, /**< SYSINFO_FEATURES  (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
-  SYSINFO_SOC_MEM_EXT        =  1, /**< SYSINFO_FEATURES  (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
-  SYSINFO_SOC_MEM_INT_IMEM   =  2, /**< SYSINFO_FEATURES  (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
-  SYSINFO_SOC_MEM_INT_DMEM   =  3, /**< SYSINFO_FEATURES  (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
-  SYSINFO_SOC_MEM_EXT_ENDIAN =  4, /**< SYSINFO_FEATURES  (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */
-  SYSINFO_SOC_ICACHE         =  5, /**< SYSINFO_FEATURES  (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
-  SYSINFO_SOC_DCACHE         =  6, /**< SYSINFO_FEATURES  (6) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
+  SYSINFO_SOC_BOOTLOADER     =  0, /**< SYSINFO_SOC  (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
+  SYSINFO_SOC_MEM_EXT        =  1, /**< SYSINFO_SOC  (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
+  SYSINFO_SOC_MEM_INT_IMEM   =  2, /**< SYSINFO_SOC  (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
+  SYSINFO_SOC_MEM_INT_DMEM   =  3, /**< SYSINFO_SOC  (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
+  SYSINFO_SOC_MEM_EXT_ENDIAN =  4, /**< SYSINFO_SOC  (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */
+  SYSINFO_SOC_ICACHE         =  5, /**< SYSINFO_SOC  (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
+  SYSINFO_SOC_DCACHE         =  6, /**< SYSINFO_SOC  (6) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */

-  SYSINFO_SOC_IO_CRC         = 12, /**< SYSINFO_FEATURES (12) (r/-):Cyclic redundancy check unit implemented when 1 (via IO_CRC_EN generic) */
-  SYSINFO_SOC_IO_SLINK       = 13, /**< SYSINFO_FEATURES (13) (r/-): Stream link interface implemented when 1 (via IO_SLINK_EN generic) */
-  SYSINFO_SOC_IO_DMA         = 14, /**< SYSINFO_FEATURES (14) (r/-): Direct memory access controller implemented when 1 (via IO_DMA_EN generic) */
-  SYSINFO_SOC_IO_GPIO        = 15, /**< SYSINFO_FEATURES (15) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
-  SYSINFO_SOC_IO_MTIME       = 16, /**< SYSINFO_FEATURES (16) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
-  SYSINFO_SOC_IO_UART0       = 17, /**< SYSINFO_FEATURES (17) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */
-  SYSINFO_SOC_IO_SPI         = 18, /**< SYSINFO_FEATURES (18) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */
-  SYSINFO_SOC_IO_TWI         = 19, /**< SYSINFO_FEATURES (19) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
-  SYSINFO_SOC_IO_PWM         = 20, /**< SYSINFO_FEATURES (20) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
-  SYSINFO_SOC_IO_WDT         = 21, /**< SYSINFO_FEATURES (21) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
-  SYSINFO_SOC_IO_CFS         = 22, /**< SYSINFO_FEATURES (22) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
-  SYSINFO_SOC_IO_TRNG        = 23, /**< SYSINFO_FEATURES (23) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
-  SYSINFO_SOC_IO_SDI         = 24, /**< SYSINFO_FEATURES (24) (r/-): Serial data interface implemented when 1 (via IO_SDI_EN generic) */
-  SYSINFO_SOC_IO_UART1       = 25, /**< SYSINFO_FEATURES (25) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
-  SYSINFO_SOC_IO_NEOLED      = 26, /**< SYSINFO_FEATURES (26) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
-  SYSINFO_SOC_IO_XIRQ        = 27, /**< SYSINFO_FEATURES (27) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
-  SYSINFO_SOC_IO_GPTMR       = 28, /**< SYSINFO_FEATURES (28) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */
-  SYSINFO_SOC_IO_XIP         = 29, /**< SYSINFO_FEATURES (29) (r/-): Execute in place module implemented when 1 (via IO_XIP_EN generic) */
-  SYSINFO_SOC_IO_ONEWIRE     = 30, /**< SYSINFO_FEATURES (30) (r/-): 1-wire interface controller implemented when 1 (via IO_ONEWIRE_EN generic) */
-  SYSINFO_SOC_OCD            = 31  /**< SYSINFO_FEATURES (31) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
+  SYSINFO_SOC_IO_CRC         = 12, /**< SYSINFO_SOC (12) (r/-):Cyclic redundancy check unit implemented when 1 (via IO_CRC_EN generic) */
+  SYSINFO_SOC_IO_SLINK       = 13, /**< SYSINFO_SOC (13) (r/-): Stream link interface implemented when 1 (via IO_SLINK_EN generic) */
+  SYSINFO_SOC_IO_DMA         = 14, /**< SYSINFO_SOC (14) (r/-): Direct memory access controller implemented when 1 (via IO_DMA_EN generic) */
+  SYSINFO_SOC_IO_GPIO        = 15, /**< SYSINFO_SOC (15) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
+  SYSINFO_SOC_IO_MTIME       = 16, /**< SYSINFO_SOC (16) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
+  SYSINFO_SOC_IO_UART0       = 17, /**< SYSINFO_SOC (17) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */
+  SYSINFO_SOC_IO_SPI         = 18, /**< SYSINFO_SOC (18) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */
+  SYSINFO_SOC_IO_TWI         = 19, /**< SYSINFO_SOC (19) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
+  SYSINFO_SOC_IO_PWM         = 20, /**< SYSINFO_SOC (20) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
+  SYSINFO_SOC_IO_WDT         = 21, /**< SYSINFO_SOC (21) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
+  SYSINFO_SOC_IO_CFS         = 22, /**< SYSINFO_SOC (22) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
+  SYSINFO_SOC_IO_TRNG        = 23, /**< SYSINFO_SOC (23) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
+  SYSINFO_SOC_IO_SDI         = 24, /**< SYSINFO_SOC (24) (r/-): Serial data interface implemented when 1 (via IO_SDI_EN generic) */
+  SYSINFO_SOC_IO_UART1       = 25, /**< SYSINFO_SOC (25) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
+  SYSINFO_SOC_IO_NEOLED      = 26, /**< SYSINFO_SOC (26) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
+  SYSINFO_SOC_IO_XIRQ        = 27, /**< SYSINFO_SOC (27) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
+  SYSINFO_SOC_IO_GPTMR       = 28, /**< SYSINFO_SOC (28) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */
+  SYSINFO_SOC_IO_XIP         = 29, /**< SYSINFO_SOC (29) (r/-): Execute in place module implemented when 1 (via IO_XIP_EN generic) */
+  SYSINFO_SOC_IO_ONEWIRE     = 30, /**< SYSINFO_SOC (30) (r/-): 1-wire interface controller implemented when 1 (via IO_ONEWIRE_EN generic) */
+  SYSINFO_SOC_OCD            = 31  /**< SYSINFO_SOC (31) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
 };

 /** NEORV32_SYSINFO->CACHE (r/-): Cache configuration */
--- a/sw/lib/source/neorv32_rte.c
+++ b/sw/lib/source/neorv32_rte.c
@ -206,7 +206,7 @@ static void __neorv32_rte_debug_handler(void) {
  // intro
  neorv32_uart0_puts("<RTE> ");

-  // privilege level of the CPU when the trap occured
+  // privilege level of the CPU when the trap occurred
  if (neorv32_cpu_csr_read(CSR_MSTATUS) & (3 << CSR_MSTATUS_MPP_L)) {
    neorv32_uart0_puts("[M] "); // machine-mode
  }
@ -297,7 +297,7 @@ void neorv32_rte_print_hw_config(void) {
  neorv32_uart0_printf("\n\n<< NEORV32 Processor Configuration >>\n");

  // CPU configuration
-  neorv32_uart0_printf("\n== Core ==\n");
+  neorv32_uart0_printf("\n==== Core ====\n");

  // general
  neorv32_uart0_printf("Is simulation:     "); __neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_IS_SIM));
@ -404,22 +404,20 @@ void neorv32_rte_print_hw_config(void) {


  // Memory configuration
-  neorv32_uart0_printf("\n\n== Memory ==\n");
+  neorv32_uart0_printf("\n\n==== Memory ====\n");

  neorv32_uart0_printf("Boot configuration:  Boot ");
  if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_BOOTLOADER)) {
    neorv32_uart0_printf("via Bootloader\n");
  }
  else {
-    neorv32_uart0_printf("from memory (@ 0x%x)\n", NEORV32_SYSINFO->ISPACE_BASE);
+    neorv32_uart0_printf("from memory\n");
  }

-  neorv32_uart0_printf("Instr. base address: 0x%x\n", NEORV32_SYSINFO->ISPACE_BASE);
-
  // internal IMEM
  neorv32_uart0_printf("Internal IMEM:       ");
  if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_INT_IMEM)) {
-    neorv32_uart0_printf("%u bytes\n", NEORV32_SYSINFO->IMEM_SIZE);
+    neorv32_uart0_printf("%u bytes\n", (uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_IMEM]) & 0xFFFFFFFCUL);
  }
  else {
    neorv32_uart0_printf("none\n");
@ -454,10 +452,9 @@ void neorv32_rte_print_hw_config(void) {
  }

  // internal DMEM
-  neorv32_uart0_printf("Data base address:   0x%x\n", NEORV32_SYSINFO->DSPACE_BASE);
  neorv32_uart0_printf("Internal DMEM:       ");
  if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_INT_DMEM)) {
-    neorv32_uart0_printf("%u bytes\n", NEORV32_SYSINFO->DMEM_SIZE);
+    neorv32_uart0_printf("%u bytes\n", (uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_DMEM]) & 0xFFFFFFFCUL);
  }
  else {
    neorv32_uart0_printf("none\n");
@ -479,6 +476,10 @@ void neorv32_rte_print_hw_config(void) {
    neorv32_uart0_printf("none\n");
  }

+  // reservation set granularity --
+  neorv32_uart0_printf("Reservation set:     ");
+    neorv32_uart0_printf("%u bytes granularity\n", (uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_RVSG]) & 0xFFFFFFFCUL);
+
  // external bus interface
  neorv32_uart0_printf("Ext. bus interface:  ");
  __neorv32_rte_print_true_false(NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_EXT));
@ -491,7 +492,7 @@ void neorv32_rte_print_hw_config(void) {
  }

  // peripherals
-  neorv32_uart0_printf("\n== Peripherals ==\n");
+  neorv32_uart0_printf("\n==== Peripherals ====\n");

  tmp = NEORV32_SYSINFO->SOC;
  __neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_GPIO));    neorv32_uart0_printf(" GPIO\n");
--- a/sw/svd/neorv32.svd
+++ b/sw/svd/neorv32.svd
@ -1508,10 +1508,16 @@
          <access>read-only</access>
        </register>
        <register>
-          <name>SYSINFO_reserved</name>
-          <description>reserved</description>
+          <name>MEM</name>
+          <description>Memory configuration (sizes)</description>
          <addressOffset>0x04</addressOffset>
          <access>read-only</access>
+          <fields>
+            <field><name>SYSINFO_MEM_0</name><bitRange>[7:0]</bitRange><description>log2(IMEM size in bytes)</description></field>
+            <field><name>SYSINFO_MEM_1</name><bitRange>[15:8]</bitRange><description>log2(DMEM size in bytes)</description></field>
+            <field><name>SYSINFO_MEM_2</name><bitRange>[23:16]</bitRange><description>reserved</description></field>
+            <field><name>SYSINFO_MEM_3</name><bitRange>[31:24]</bitRange><description>log2(reservation set granulartiy in bytes)</description></field>
+          </fields>
        </register>
        <register>
          <name>SOC</name>
@ -1560,30 +1566,6 @@
            <field><name>SYSINFO_CACHE_IC_REPLACEMENT</name><bitRange>[15:12]</bitRange><description>i-cache: replacement policy (0001 = LRU if associativity > 0)</description></field>
          </fields>
        </register>
-        <register>
-          <name>ISPACE_BASE</name>
-          <description>Instruction memory address space base address</description>
-          <addressOffset>0x10</addressOffset>
-          <access>read-only</access>
-        </register>
-        <register>
-          <name>DSPACE_BASE</name>
-          <description>Data memory address space base address</description>
-          <addressOffset>0x14</addressOffset>
-          <access>read-only</access>
-        </register>
-        <register>
-          <name>IMEM_SIZE</name>
-          <description>Internal instruction memory (IMEM) size in bytes</description>
-          <addressOffset>0x18</addressOffset>
-          <access>read-only</access>
-        </register>
-        <register>
-          <name>DMEM_SIZE</name>
-          <description>Internal data memory (DMEM) size in bytes</description>
-          <addressOffset>0x1C</addressOffset>
-          <access>read-only</access>
-        </register>
      </registers>
    </peripheral>