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🚀 preparing release v1.9.4

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stnolting 2024-01-31 20:46:03 +01:00
parent e3dde60624
commit 6269bd2fcd
3 changed files with 3 additions and 2 deletions
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1
CHANGELOG.md
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@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Link |
|:----:|:-------:|:--------|:----:|
| 31.01.2024 | [**:rocket:1.9.4**](https://github.com/stnolting/neorv32/releases/tag/v1.9.4) | **New release** | |
| 31.01.2024 | 1.9.3.10 | close illegal compressed instruction decoding loophole | [#783](https://github.com/stnolting/neorv32/pull/783) |
| 29.01.2024 | 1.9.3.9 | :test_tube: extend switchable clock domain (CPU bus switch, i-cache, d-cache) | [#780](https://github.com/stnolting/neorv32/pull/780) |
| 29.01.2024 | 1.9.3.8 | top entity input ports now have default values `'L'` or `'h'` modeling a pull-down or pull-resistor in case they are not explicitly assigned during instantiation | [#779](https://github.com/stnolting/neorv32/pull/779) |

2
rtl/core/neorv32_package.vhd
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@ -56,7 +56,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090310"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090400"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

2
sw/svd/neorv32.svd
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@ -4,7 +4,7 @@
<vendor>stnolting</vendor>
<name>neorv32</name>
<series>RISC-V</series>
<version>1.9.3</version>
<version>1.9.4</version>
<description>The NEORV32 RISC-V Processor</description>
<!-- CPU core -->