minor edits, typo fixes and clean-ups

.gitignore

@@ -4,6 +4,7 @@
 *.elf
 *.asm
 *.out
+*.hex
 *_image.vhd
 
 # keep default VHDL memory images

CHANGELOG.md

@@ -24,7 +24,7 @@ defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:----------:|:-------:|:--------|
-| 03.07.2021 | 1.5.7.10 | :sparkles: added new component: External Interrupt Controller (XIRQ): up to 32 external interrupt channels `xirq_i` (via `XIRQ_NUM_CH` generic), configurable trigger (via `XIRQ_TRIGGER_TYPE` and `XIRQ_TRIGGER_POLARITY` generics), prioritized or non-prioritized servicing |
+| 03.07.2021 | 1.5.7.10 | :sparkles: added new component: **External Interrupt Controller (XIRQ)**: up to 32 external interrupt channels `xirq_i` (via `XIRQ_NUM_CH` generic), configurable trigger (via `XIRQ_TRIGGER_TYPE` and `XIRQ_TRIGGER_POLARITY` generics), prioritized or non-prioritized servicing |
 | 02.07.2021 | 1.5.7.9 | relocated base addresses of watchdog timer (WDT) and true-random number generator (TRNG); removed CPU's `firq_ack_o` signal (was not used at all) |
 | 30.06.2021 | 1.5.7.8 | :warning: increased GPIO port size from 32-bit to 64-bit; relocated GPIO base address; removed GPIO.input pin-change interrupt |
 | 29.06.2021 | 1.5.7.7 | :sparkles: added new processor module **stream link interface (SLINK)**: up to 8 individual RX and TX stream links, comptaible to AXI4-Stream base protocol; added software driver files; added documentation |

rtl/core/neorv32_package.vhd

@@ -50,7 +50,7 @@ package neorv32_package is
   constant wb_rx_buffer_c  : boolean := true;  -- use register buffer for RX data when true (default)
 
   -- CPU core --
-  constant ipb_entries_c     : natural := 4; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
+  constant ipb_entries_c     : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
   constant cp_timeout_en_c   : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
   constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
 

rtl/core/neorv32_xirq.vhd

@@ -2,7 +2,7 @@
 -- # << NEORV32 - External Interrupt Controller (XIRQ) >>                                          #
 -- # ********************************************************************************************* #
 -- # Simple interrupt controller for platform (processor-external) interrupts. Up to 32 channels   #
--- # are supported that get prioritized into a single CPU interrupt.                               #
+-- # are supported that get (optionally) prioritized into a single CPU interrupt.                  #
 -- #                                                                                               #
 -- # The actual trigger configuration has to be done before synthesis using the XIRQ_TRIGGER_TYPE  #
 -- # and XIRQ_TRIGGER_POLARITY generics. These allow to configure channel-independent low-level,   #

sw/example/demo_xirq/main.c

@@ -36,7 +36,7 @@
 /**********************************************************************//**
  * @file demo_xirq/main.c
  * @author Stephan Nolting
- * @brief External interrupt controller (XIRQ) demo program.
+ * @brief External interrupt controller (XIRQ) demo program (using hardware-assisted prioritization).
  **************************************************************************/
 
 #include <neorv32.h>
@@ -139,12 +139,17 @@ int main() {
   }
 
 
-  // wait for interrupts
+  // --- wait for interrupts ---
+  // All incoming XIRQ interrupt requests are "prioritized" in this example. The XIRQ FIRQ handler
+  // reads the ID of the interrupt with the highest priority from the XIRQ controller ("source" register) and calls the according
+  // handler function.
+  // Non-prioritized handling of interrupts (or custom prioritization) can be implemented by manually reading the
+  // XIRQ controller's "pending" register. It is up to the software to define which pending IRQ should be served.
   while(1);
 
 
   // just as an example: to disable certain XIRQ interrupt channels, we can
-  // uninstall the according handler. this will also clear a pending interrupt for that channel
+  // un-install the according handler. this will also clear a pending interrupt for that channel
   neorv32_xirq_uninstall(0); // disable XIRQ channel 0 and remove associated handler
   neorv32_xirq_uninstall(1); // disable XIRQ channel 1 and remove associated handler
   neorv32_xirq_uninstall(2); // disable XIRQ channel 2 and remove associated handler

sw/lib/include/neorv32_cpu.h

@@ -66,7 +66,7 @@ int neorv32_cpu_check_zext(uint8_t flag_id);
  * @param[in] return_code Return value of main() function.
  * @return Return value is irrelevant (there is no one left to check for it...).
  **************************************************************************/
-extern int __neorv32_crt0_after_main(int32_t return_code);
+extern int __neorv32_crt0_after_main(int32_t return_code) __attribute__ ((weak));
 
 
 /**********************************************************************//**