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minor optimization

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stnolting 2020-09-11 19:22:11 +02:00
parent d991ae8b84
commit 6940ea3caa
2 changed files with 5 additions and 5 deletions
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6
rtl/core/neorv32_package.vhd
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@ -38,7 +38,7 @@ use ieee.numeric_std.all;
package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- Architecture Constants/Configuration ---------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - FIXED!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040004"; -- no touchy!
@ -62,7 +62,7 @@ package neorv32_package is
type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
-- Processor-internal Address Space Layout ------------------------------------------------
-- Processor-Internal Address Space Layout ------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Instruction Memory & Data Memory --
-- => configured via top's generics
@ -127,7 +127,7 @@ package neorv32_package is
-- True Random Number generator (TRNG) --
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
constant trng_size_c : natural := 2*4; -- bytes, fixed!
constant trng_size_c : natural := 1*4; -- bytes, fixed!
constant trng_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000");
-- RESERVED --

4
rtl/core/neorv32_trng.vhd
View file

@ -152,12 +152,12 @@ begin
if rising_edge(clk_i) then
ack_o <= acc_en and (rden_i or wren_i);
-- write access --
if (wren = '1') and (addr = trng_ctrl_addr_c) then
if (wren = '1') then
rnd_enable <= data_i(ctrl_en_c);
end if;
-- read access --
data_o <= (others => '0');
if (rden = '1') and (addr = trng_ctrl_addr_c) then
if (rden = '1') then
data_o(ctrl_data_msb_c downto ctrl_data_lsb_c) <= rnd_output;
data_o(ctrl_data_valid_c) <= rnd_ready;
data_o(ctrl_err_zero_c) <= rnd_error_zero;