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[docs] added notes regarding platform-specific memory mapping optimization

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stnolting 2021-06-12 22:01:51 +02:00
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5
docs/datasheet/soc_bootrom.adoc
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@ -12,6 +12,11 @@
| CPU interrupts: | none |
|=======================
[NOTE]
The default `neorv32_boot_rom.vhd` HDL source file provides a _generic_ memory design that infers embedded
memory. You might need to replace/modify the source file in order to use platform-specific features
(like advanced memory resources) or to improve technology mapping and/or timing.
As the name already suggests, the boot ROM contains the read-only bootloader image. When the bootloader
is enabled via the _BOOTLOADER_EN_ generic it is directly executed after system reset.

5
docs/datasheet/soc_dmem.adoc
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@ -13,6 +13,11 @@
| CPU interrupts: | none |
|=======================
[NOTE]
The default `neorv32_dmem.vhd` HDL source file provides a _generic_ memory design that infers embedded
memory. You might need to replace/modify the source file in order to use platform-specific features
(like advanced memory resources) or to improve technology mapping and/or timing.
Implementation of the processor-internal data memory is enabled via the processor's _MEM_INT_DMEM_EN_
generic. The size in bytes is defined via the _MEM_INT_DMEM_SIZE_ generic. If the DMEM is implemented,
the memory is mapped into the data memory space and located right at the beginning of the data memory

5
docs/datasheet/soc_icache.adoc
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@ -15,6 +15,11 @@
| CPU interrupts: | none |
|=======================
[NOTE]
The default `neorv32_icache.vhd` HDL source file provides a _generic_ memory design that infers embedded
memory. You might need to replace/modify the source file in order to use platform-specific features
(like advanced memory resources) or to improve technology mapping and/or timing.
The processor features an optional cache for instructions to compensate memories with high latency. The
cache is directly connected to the CPU's instruction fetch interface and provides a full-transparent buffering
of instruction fetch accesses to the entire 4GB address space.

5
docs/datasheet/soc_imem.adoc
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@ -14,6 +14,11 @@
| CPU interrupts: | none |
|=======================
[NOTE]
The default `neorv32_imem.vhd` HDL source file provides a _generic_ memory design that infers embedded
memory. You might need to replace/modify the source file in order to use platform-specific features
(like advanced memory resources) or to improve technology mapping and/or timing.
Implementation of the processor-internal instruction memory is enabled via the processor's
_MEM_INT_IMEM_EN_ generic. The size in bytes is defined via the _MEM_INT_IMEM_SIZE_ generic. If the
IMEM is implemented, the memory is mapped into the instruction memory space and located right at the