Merge branch 'main' into fix_atomic_csr_clearing

README.md

@@ -84,7 +84,7 @@ The processor passes the official RISC-V architecture tests to ensure compatibil
 [neorv32-riscof](https://github.com/stnolting/neorv32-riscof) repository. It can successfully run _any_ C program
 (for example from the [`sw/example`](https://github.com/stnolting/neorv32/tree/main/sw/example) folder) including CoreMark
 and FreeRTOS and can be synthesized for _any_ target technology - [tested](https://github.com/stnolting/neorv32-setups)
-on Intel, Xilinx and Lattice FPGAs. The conversion into a plain-Verilog netlist module is automatically checked by the
+on Intel, AMD and Lattice FPGAs. The conversion into a plain-Verilog netlist module is automatically checked by the
 [neorv32-verilog](https://github.com/stnolting/neorv32-verilog) repository.
 
 [[_back to top_](#the-neorv32-risc-v-processor)]

docs/legal.adoc

@@ -46,7 +46,7 @@ stnolting@gmail.com
 === Proprietary Notice
 
 * "GitHub" is a Subsidiary of Microsoft Corporation.
-* "Vivado" and "Artix" are trademarks of Xilinx Inc.
+* "Vivado" and "Artix" are trademarks of AMD Inc.
 * "AXI", "AXI4-Lite" and "AXI4-Stream" are trademarks of Arm Holdings plc.
 * "ModelSim" is a trademark of Mentor Graphics – A Siemens Business.
 * "Quartus Prime" and "Cyclone" are trademarks of Intel Corporation.

docs/userguide/adding_custom_hw_modules.adoc

@@ -39,7 +39,7 @@ AXI4-Lite or Intel's Avalon protocols. By using a full-featured bus protocol, co
 including several modules and even multi-core architectures. Many FPGA EDA tools provide graphical editors to build
 and customize whole SoC architectures and even include pre-defined IP libraries.
 
-.Example AXI SoC using Xilinx Vivado
+.Example AXI SoC using AMD Vivado
 image::neorv32_axi_soc.png[]
 
 Custom hardware modules attached to the processor's bus interface have no limitations regarding their functionality.

docs/userguide/neorv32_in_verilog.adoc

@@ -32,7 +32,7 @@ module neorv32_verilog_wrapper
 
 The generated Verilog netlist has been tested with
 https://github.com/steveicarus/iverilog[Icarus Verilog]
-(simulation) and Xilinx Vivado (simulation and synthesis).
+(simulation) and AMD Vivado (simulation and synthesis).
 
 [TIP]
 For detailed information check out the `neorv32-verilog` repository at https://github.com/stnolting/neorv32-verilog.

docs/userguide/packaging_vivado.adoc

@@ -30,6 +30,15 @@ footnote:[Seems like Vivado has problem evaluating design source files that have
 If the TRNG is not needed, you can disable it by double-clicking on the module's block and de-selecting
 "IO_TRNG_EN" after inserting the module.
 
+.SLINK AXI4-Stream Interfaces
+[IMPORTANT]
+The SLINK peripheral's input and output streams are exposed as AXI4-Stream compatible interfaces in the
+`rtl/system_integration/neorv32_top_axi4lite.vhd` top-level module. These interfaces provide clock inputs for
+each of the streams, so that they can be connected to an appropriate clock source to satisfy Vivado's
+validation for compatible clocks on each end of the stream connection. However, these clock inputs are not presently
+used internally to the core, and using streams clocked on a clock domain other than that connected to m_axi_aclk is NOT
+presently supported - doing this will result in timing failures or improper operation.
+
 **Combinatorial Loops DRC error**
 If the TRNG is enabled it is recommended to add the following commands to the project's constraints file in order
 to prevent DRC errors during bitstream generation:

docs/userguide/simulating_the_processor.adoc

@@ -12,9 +12,9 @@ That is used for running the RISC-V architecture tests, in order to guarantee co
 On the other hand, http://vunit.github.io/[VUnit] and http://vunit.github.io/verification_components/user_guide.html[Verification Components]
 are used for verifying the functionality of the various peripherals from a hardware point of view.
 
-.Xilinx Vivado / ISIM
+.AMD Vivado / ISIM
 [IMPORTANT]
-When using Xilinx Vivado (ISIM for simulation) make sure to **turn of** "incremental compilation" (_Project Setting_
+When using AMD Vivado (ISIM for simulation) make sure to **turn of** "incremental compilation" (_Project Setting_
 -> _Simulation_ -> _Advanced_ -> _Enable incremental compilation). This will slow down simulation relaunch but will
 ensure that all application images (`*_image.vhd`) are reanalyzed when recompiling the NEORV32 application or bootloader
 

rtl/core/neorv32_cpu_decompressor.vhd

@@ -2,7 +2,7 @@
 -- # << NEORV32 CPU - Compressed Instructions Decoder (RISC-V "C" Extension) >>                    #
 -- # ********************************************************************************************* #
 -- # Compressed instructions decoder compatible to the RISC-V C ISA extension. Illegal compressed  #
--- # instructions are otuput "as-is".                                                              #
+-- # instructions are output "as-is".                                                              #
 -- # ********************************************************************************************* #
 -- # BSD 3-Clause License                                                                          #
 -- #                                                                                               #

rtl/system_integration/neorv32_SystemTop_axi4lite.vhd

@@ -171,11 +171,13 @@ entity neorv32_SystemTop_axi4lite is
     s0_axis_tvalid : out std_logic;
     s0_axis_tlast  : out std_logic;
     s0_axis_tready : in  std_logic;
+    s0_axis_aclk   : in  std_logic; -- present to satisfy Vivado, not used!
     -- Sink --
     s1_axis_tdata  : in  std_logic_vector(31 downto 0);
     s1_axis_tvalid : in  std_logic;
     s1_axis_tlast  : in  std_logic;
     s1_axis_tready : out std_logic;
+    s1_axis_aclk   : in  std_logic; -- present to satisfy Vivado, not used!
     -- ------------------------------------------------------------
     -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
     -- ------------------------------------------------------------
@@ -616,7 +618,7 @@ begin
   -- AXI4-Lite Read Address Channel --
   m_axi_araddr  <= std_logic_vector(wb_core.adr);
   m_axi_arvalid <= std_logic((wb_core.cyc and (not wb_core.we)) and (not ctrl.radr_received));
---m_axi_arprot  <= "000"; -- recommended by Xilinx
+--m_axi_arprot  <= "000"; -- recommended by AMD
   m_axi_arprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access
   m_axi_arprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access
   m_axi_arprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access
@@ -630,7 +632,7 @@ begin
   -- AXI4-Lite Write Address Channel --
   m_axi_awaddr  <= std_logic_vector(wb_core.adr);
   m_axi_awvalid <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wadr_received));
---m_axi_awprot  <= "000"; -- recommended by Xilinx
+--m_axi_awprot  <= "000"; -- recommended by AMD
   m_axi_awprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access
   m_axi_awprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access
   m_axi_awprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access