mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-23 21:57:33 -04:00
[sim] split ghdl setup and run
This commit is contained in:
umarcor
parent
dd079dfdbb
commit
6d59641493
11 changed files with 215 additions and 189 deletions
2
.github/workflows/Processor.yml
vendored
2
.github/workflows/Processor.yml
vendored
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@ -52,7 +52,7 @@ jobs:
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run: ./sw/example/processor_check/check.sh
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- name: '🚧 Run Processor Hardware Tests with shell script'
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run: ./sim/ghdl_sim.sh
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run: ./sim/ghdl.sh
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VUnit-Container:
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40
sim/ghdl.run.sh
Executable file
40
sim/ghdl.run.sh
Executable file
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@ -0,0 +1,40 @@
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#!/usr/bin/env bash
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set -e
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cd $(dirname "$0")
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echo "Tip: Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to auto-enable UART[0/1]'s simulation mode (redirect UART output to simulator console)."
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# Prepare simulation output files for UART0 and UART 1
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# - Testbench receiver log file (neorv32.testbench_uart?.out)
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# - Direct simulation output (neorv32.uart?.sim_mode.[text|data].out)
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for uart in 0 1; do
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for item in \
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testbench_uart"$uart" \
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uart"$uart".sim_mode.text \
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uart"$uart".sim_mode.data; do
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touch neorv32."$item".out
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chmod 777 neorv32."$item".out
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done
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done
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GHDL="${GHDL:-ghdl}"
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$GHDL -m --work=neorv32 --workdir=build neorv32_tb_simple
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GHDL_RUN_ARGS="${@:---stop-time=10ms}"
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echo "Using simulation runtime args: $GHDL_RUN_ARGS";
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runcmd="$GHDL -r --work=neorv32 --workdir=build neorv32_tb_simple \
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--max-stack-alloc=0 \
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--ieee-asserts=disable \
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--assert-level=error $GHDL_RUN_ARGS"
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if [ -n "$GHDL_DEVNULL" ]; then
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$runcmd >> /dev/null
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else
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$runcmd
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fi
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cat neorv32.uart0.sim_mode.text.out | grep "CPU TEST COMPLETED SUCCESSFULLY!"
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14
sim/ghdl.setup.sh
Executable file
14
sim/ghdl.setup.sh
Executable file
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@ -0,0 +1,14 @@
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#!/usr/bin/env bash
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set -e
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cd $(dirname "$0")
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mkdir -p build
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ghdl -i --work=neorv32 --workdir=build \
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../rtl/core/*.vhd \
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../rtl/templates/processor/*.vhd \
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../rtl/templates/system/*.vhd \
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neorv32_tb.simple.vhd \
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uart_rx.simple.vhd
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14
sim/ghdl.sh
Executable file
14
sim/ghdl.sh
Executable file
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@ -0,0 +1,14 @@
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#!/usr/bin/env bash
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# `GHDL` is used to check all VHDL files for syntax errors and to simulate the default testbench. The previously
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# installed CPU test program is executed and the console output (UART0 primary UART) is dumped to a text file. After the
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# simulation has finished, the text file is searched for a specific string. If the string is found, the CPU test was
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# successful.
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# Abort if any command returns != 0
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set -e
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cd $(dirname "$0")
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./ghdl.setup.sh
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./ghdl.run.sh
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@ -1,52 +0,0 @@
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#!/usr/bin/env bash
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# `GHDL` is used to check all VHDL files for syntax errors and to simulate the default testbench. The previously
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# installed CPU test program is executed and the console output (UART0 primary UART) is dumped to a text file. After the
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# simulation has finished, the text file is searched for a specific string. If the string is found, the CPU test was
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# successful.
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# Abort if any command returns != 0
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set -e
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cd $(dirname "$0")
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# Simulation configuration
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SIM_CONFIG=--stop-time=10ms
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if [ -n "$1" ]; then
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SIM_CONFIG="$1";
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fi
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echo "Using simulation config: $SIM_CONFIG";
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echo "Tip: Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to auto-enable UART[0/1]'s simulation mode (redirect UART output to simulator console)."
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mkdir -p build
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# Analyse sources; libs and images at first!
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ghdl -i --work=neorv32 --workdir=build \
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../rtl/core/*.vhd \
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../rtl/templates/processor/*.vhd \
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../rtl/templates/system/*.vhd \
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neorv32_tb.simple.vhd \
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uart_rx.simple.vhd
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# Prepare simulation output files for UART0 and UART 1
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# - Testbench receiver log file (neorv32.testbench_uart?.out)
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# - Direct simulation output (neorv32.uart?.sim_mode.[text|data].out)
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for item in \
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testbench_uart0 \
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uart0.sim_mode.text \
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uart0.sim_mode.data \
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testbench_uart1 \
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uart1.sim_mode.text \
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uart1.sim_mode.data; do
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touch neorv32."$item".out
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chmod 777 neorv32."$item".out
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done
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# Run simulation
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ghdl -m --work=neorv32 --workdir=build neorv32_tb_simple
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ghdl -r --work=neorv32 --workdir=build neorv32_tb_simple --max-stack-alloc=0 --ieee-asserts=disable --assert-level=error $SIM_CONFIG
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cat neorv32.uart0.sim_mode.text.out | grep "CPU TEST COMPLETED SUCCESSFULLY!"
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rm -rf *.{o,cf,lst,out} build
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@ -33,7 +33,7 @@ mkdir -p work/sim
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for item in 'rtl' 'sw'; do
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cp -r ../"$item" work
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done
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for item in *.simple.vhd ghdl_sim.sh; do
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for item in *.simple.vhd ghdl*.sh; do
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cp -r "$item" work/sim
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done
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@ -9,33 +9,6 @@ ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
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$(error Target simulator executable '$(TARGET_SIM)` not found)
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endif
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RUN_TARGET=\
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cd $(work_dir_isa); \
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rm -f $(NEORV32_LOCAL_COPY)/*.out; \
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echo "copying/using SIM-only IMEM (ROM!)"; \
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rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
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cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
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cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
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make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \
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make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
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touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
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$(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
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cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
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RISCV_PREFIX ?= riscv32-unknown-elf-
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RISCV_GCC ?= $(RISCV_PREFIX)gcc
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RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
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@ -50,3 +23,32 @@ COMPILE_TARGET=\
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-I$(TARGETDIR)/$(RISCV_TARGET)/ \
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-T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_rom.ld \
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$$(<) -o $$@
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RUN_TARGET=\
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cd $(work_dir_isa); \
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echo ">"; \
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rm -f $(NEORV32_LOCAL_COPY)/*.out; \
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echo "copying/using SIM-only IMEM (ROM!)"; \
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rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
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cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
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sed -i \
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-e '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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$(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
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cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
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make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin install; \
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touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
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GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl.run.sh --stop-time=$(SIM_TIME); \
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cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output; \
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echo "<";
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@ -9,33 +9,6 @@ ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
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$(error Target simulator executable '$(TARGET_SIM)` not found)
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endif
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RUN_TARGET=\
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cd $(work_dir_isa); \
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rm -f $(NEORV32_LOCAL_COPY)/*.out; \
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echo "copying/using SIM-only IMEM (ROM!)"; \
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rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
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cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
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make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
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cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
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make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \
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make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
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touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
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$(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
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cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
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RISCV_PREFIX ?= riscv32-unknown-elf-
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RISCV_GCC ?= $(RISCV_PREFIX)gcc
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RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
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@ -50,3 +23,32 @@ COMPILE_TARGET=\
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-I$(TARGETDIR)/$(RISCV_TARGET)/ \
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-T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_rom.ld \
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$$(<) -o $$@
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RUN_TARGET=\
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cd $(work_dir_isa); \
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echo ">"; \
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rm -f $(NEORV32_LOCAL_COPY)/*.out; \
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echo "copying/using SIM-only IMEM (ROM!)"; \
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rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
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cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
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sed -i \
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-e '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
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-e '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
$(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
|
||||
cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl.run.sh --stop-time=$(SIM_TIME); \
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output; \
|
||||
echo "<";
|
||||
|
|
|
|||
|
|
@ -9,33 +9,6 @@ ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
|
|||
$(error Target simulator executable '$(TARGET_SIM)` not found)
|
||||
endif
|
||||
|
||||
RUN_TARGET=\
|
||||
cd $(work_dir_isa); \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "copying/using SIM-only IMEM (ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
|
||||
cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
$(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
RISCV_GCC ?= $(RISCV_PREFIX)gcc
|
||||
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
|
||||
|
|
@ -50,3 +23,32 @@ COMPILE_TARGET=\
|
|||
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
|
||||
-T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_rom.ld \
|
||||
$$(<) -o $$@
|
||||
|
||||
RUN_TARGET=\
|
||||
cd $(work_dir_isa); \
|
||||
echo ">"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "copying/using SIM-only IMEM (ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i \
|
||||
-e '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
$(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
|
||||
cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl.run.sh --stop-time=$(SIM_TIME); \
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output; \
|
||||
echo "<";
|
||||
|
|
|
|||
|
|
@ -9,33 +9,6 @@ ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
|
|||
$(error Target simulator executable '$(TARGET_SIM)` not found)
|
||||
endif
|
||||
|
||||
RUN_TARGET=\
|
||||
cd $(work_dir_isa); \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "restoring/using original IMEM rtl file"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.ORIGINAL $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 32*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
|
||||
cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
$(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
RISCV_GCC ?= $(RISCV_PREFIX)gcc
|
||||
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
|
||||
|
|
@ -50,3 +23,32 @@ COMPILE_TARGET=\
|
|||
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
|
||||
-T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_ram.ld \
|
||||
$$(<) -o $$@
|
||||
|
||||
RUN_TARGET=\
|
||||
cd $(work_dir_isa); \
|
||||
echo ">"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "restoring/using original IMEM rtl file"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.ORIGINAL $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i \
|
||||
-e '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 32*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
$(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
|
||||
cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl.run.sh --stop-time=$(SIM_TIME); \
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output; \
|
||||
echo "<";
|
||||
|
|
|
|||
|
|
@ -9,33 +9,6 @@ ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
|
|||
$(error Target simulator executable '$(TARGET_SIM)` not found)
|
||||
endif
|
||||
|
||||
RUN_TARGET=\
|
||||
cd $(work_dir_isa); \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "copying/using SIM-only IMEM (ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
|
||||
cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
$(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
RISCV_GCC ?= $(RISCV_PREFIX)gcc
|
||||
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
|
||||
|
|
@ -50,3 +23,32 @@ COMPILE_TARGET=\
|
|||
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
|
||||
-T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_rom.ld \
|
||||
$$(<) -o $$@
|
||||
|
||||
RUN_TARGET=\
|
||||
cd $(work_dir_isa); \
|
||||
echo ">"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "copying/using SIM-only IMEM (ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i \
|
||||
-e '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
-e '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' \
|
||||
$(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \
|
||||
cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \
|
||||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_LOCAL_COPY)/sim/ghdl.run.sh --stop-time=$(SIM_TIME); \
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output; \
|
||||
echo "<";
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue