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⚠️ [top] rename CPU tuning generics

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add "CPU_" prefix
This commit is contained in:
stnolting 2024-12-22 17:57:35 +01:00
parent f3c21f9767
commit 70c76d48ad
5 changed files with 73 additions and 72 deletions
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8
docs/datasheet/soc.adoc
View file

@ -243,10 +243,10 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
| `RISCV_ISA_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
| `RISCV_ISA_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).
4+^| **<<_cpu_tuning_options>>**
| `CLOCK_GATING_EN` | boolean | false | Implement sleep-mode clock gating (see sections <<_sleep_mode>> and <<_processor_clocking>>).
| `FAST_MUL_EN` | boolean | false | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.
| `FAST_SHIFT_EN` | boolean | false | Implement fast but large full-parallel barrel shifters; see section <<_cpu_arithmetic_logic_unit>>.
| `REGFILE_HW_RST` | boolean | false | Implement full hardware reset for register file (use individual FFs instead of BRAM); see section <<_cpu_register_file>>.
| `CPU_CLOCK_GATING_EN` | boolean | false | Implement sleep-mode clock gating; see sections <<_sleep_mode>> and <<_cpu_clock_gating>>.
| `CPU_FAST_MUL_EN` | boolean | false | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.
| `CPU_FAST_SHIFT_EN` | boolean | false | Implement fast but large full-parallel barrel shifters; see section <<_cpu_arithmetic_logic_unit>>.
| `CPU_REGFILE_HW_RST` | boolean | false | Implement full hardware reset for register file (use individual FFs instead of BRAM); see section <<_cpu_register_file>>.
4+^| **Physical Memory Protection (<<_smpmp_isa_extension>>)**
| `PMP_NUM_REGIONS` | natural | 0 | Number of implemented PMP regions (0..16).
| `PMP_MIN_GRANULARITY` | natural | 4 | Minimal region granularity in bytes. Has to be a power of two, min 4.

16
rtl/core/neorv32_top.vhd
View file

@ -61,10 +61,10 @@ entity neorv32_top is
RISCV_ISA_Zxcfu : boolean := false; -- implement custom (instr.) functions unit
-- Tuning Options --
CLOCK_GATING_EN : boolean := false; -- enable clock gating when in sleep mode
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
REGFILE_HW_RST : boolean := false; -- implement full hardware reset for register file
CPU_CLOCK_GATING_EN : boolean := false; -- enable clock gating when in sleep mode
CPU_FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
CPU_FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
CPU_REGFILE_HW_RST : boolean := false; -- implement full hardware reset for register file
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural range 0 to 16 := 0; -- number of regions (0..16)
@ -499,10 +499,10 @@ begin
RISCV_ISA_Sdtrig => OCD_EN,
RISCV_ISA_Smpmp => cpu_smpmp_c,
-- Tuning Options --
CLOCK_GATING_EN => CLOCK_GATING_EN,
FAST_MUL_EN => FAST_MUL_EN,
FAST_SHIFT_EN => FAST_SHIFT_EN,
REGFILE_HW_RST => REGFILE_HW_RST,
CPU_CLOCK_GATING_EN => CPU_CLOCK_GATING_EN,
CPU_FAST_MUL_EN => CPU_FAST_MUL_EN,
CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN,
CPU_REGFILE_HW_RST => CPU_REGFILE_HW_RST,
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS => PMP_NUM_REGIONS,
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY,

6
rtl/system_integration/neorv32_vivado_ip.tcl
View file

@ -247,9 +247,9 @@ proc setup_ip_gui {} {
set group [add_group $page {Tuning Options}]
add_params $group {
{ FAST_MUL_EN {DSP-Based Multiplier} }
{ FAST_SHIFT_EN {Barrel Shifter} }
{ REGFILE_HW_RST {Allow Full HW Reset for Register File} {Implement register file with FFs instead of BRAM to allow full hardware reset} }
{ CPU_FAST_MUL_EN {DSP-Based Multiplier} }
{ CPU_FAST_SHIFT_EN {Barrel Shifter} }
{ CPU_REGFILE_HW_RST {Allow Full HW Reset for Register File} {Implement register file with FFs instead of BRAM to allow full hardware reset} }
}

14
rtl/system_integration/neorv32_vivado_ip.vhd
View file

@ -60,9 +60,9 @@ entity neorv32_vivado_ip is
RISCV_ISA_Zksh : boolean := false;
RISCV_ISA_Zxcfu : boolean := false;
-- Tuning Options --
FAST_MUL_EN : boolean := false;
FAST_SHIFT_EN : boolean := false;
REGFILE_HW_RST : boolean := false;
CPU_FAST_MUL_EN : boolean := false;
CPU_FAST_SHIFT_EN : boolean := false;
CPU_REGFILE_HW_RST : boolean := false;
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural range 0 to 16 := 0;
PMP_MIN_GRANULARITY : natural := 4;
@ -387,10 +387,10 @@ begin
RISCV_ISA_Zksh => RISCV_ISA_Zksh,
RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu,
-- Extension Options --
CLOCK_GATING_EN => false, -- clock gating is not supported here
FAST_MUL_EN => FAST_MUL_EN,
FAST_SHIFT_EN => FAST_SHIFT_EN,
REGFILE_HW_RST => REGFILE_HW_RST,
CPU_CLOCK_GATING_EN => false, -- clock gating is not supported here
CPU_FAST_MUL_EN => CPU_FAST_MUL_EN,
CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN,
CPU_REGFILE_HW_RST => CPU_REGFILE_HW_RST,
-- Physical Memory Protection --
PMP_NUM_REGIONS => PMP_NUM_REGIONS,
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY,

101
sim/neorv32_tb.vhd
View file

@ -19,54 +19,55 @@ use neorv32.neorv32_package.all;
entity neorv32_tb is
generic (
-- processor --
CLOCK_FREQUENCY : natural := 100_000_000; -- clock frequency of clk_i in Hz
BOOT_MODE_SELECT : natural range 0 to 2 := 2; -- boot from pre-initialized IMEM
BOOT_ADDR_CUSTOM : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CPU boot address (if boot_config = 1)
RISCV_ISA_C : boolean := false; -- implement compressed extension
RISCV_ISA_E : boolean := false; -- implement embedded RF extension
RISCV_ISA_M : boolean := true; -- implement mul/div extension
RISCV_ISA_U : boolean := true; -- implement user mode extension
RISCV_ISA_Zalrsc : boolean := true; -- implement atomic reservation-set extension
RISCV_ISA_Zba : boolean := true; -- implement shifted-add bit-manipulation extension
RISCV_ISA_Zbb : boolean := true; -- implement basic bit-manipulation extension
RISCV_ISA_Zbkb : boolean := true; -- implement bit-manipulation instructions for cryptography
RISCV_ISA_Zbkc : boolean := true; -- implement carry-less multiplication instructions
RISCV_ISA_Zbkx : boolean := true; -- implement cryptography crossbar permutation extension
RISCV_ISA_Zbs : boolean := true; -- implement single-bit bit-manipulation extension
RISCV_ISA_Zfinx : boolean := true; -- implement 32-bit floating-point extension
RISCV_ISA_Zicntr : boolean := true; -- implement base counters
RISCV_ISA_Zicond : boolean := true; -- implement integer conditional operations
RISCV_ISA_Zihpm : boolean := true; -- implement hardware performance monitors
RISCV_ISA_Zknd : boolean := true; -- implement cryptography NIST AES decryption extension
RISCV_ISA_Zkne : boolean := true; -- implement cryptography NIST AES encryption extension
RISCV_ISA_Zknh : boolean := true; -- implement cryptography NIST hash extension
RISCV_ISA_Zksed : boolean := true; -- implement ShangMi block cypher extension
RISCV_ISA_Zksh : boolean := true; -- implement ShangMi hash extension
RISCV_ISA_Zmmul : boolean := true; -- implement multiply-only M sub-extension
RISCV_ISA_Zxcfu : boolean := true; -- implement custom (instr.) functions unit
FAST_MUL_EN : boolean := true; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := true; -- use barrel shifter for shift operations
REGFILE_HW_RST : boolean := true; -- implement full hardware reset for register file
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 32*1024; -- size of processor-internal instruction memory in bytes (use a power of 2)
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes (use a power of 2)
ICACHE_EN : boolean := true; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 64; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32; -- i-cache: block size in bytes (min 4), has to be a power of 2
DCACHE_EN : boolean := true; -- implement data cache
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 32; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32; -- d-cache: block size in bytes (min 4), has to be a power of 2
CLOCK_FREQUENCY : natural := 100_000_000; -- clock frequency of clk_i in Hz
BOOT_MODE_SELECT : natural range 0 to 2 := 2; -- boot from pre-initialized IMEM
BOOT_ADDR_CUSTOM : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CPU boot address (if boot_config = 1)
RISCV_ISA_C : boolean := false; -- implement compressed extension
RISCV_ISA_E : boolean := false; -- implement embedded RF extension
RISCV_ISA_M : boolean := true; -- implement mul/div extension
RISCV_ISA_U : boolean := true; -- implement user mode extension
RISCV_ISA_Zalrsc : boolean := true; -- implement atomic reservation-set extension
RISCV_ISA_Zba : boolean := true; -- implement shifted-add bit-manipulation extension
RISCV_ISA_Zbb : boolean := true; -- implement basic bit-manipulation extension
RISCV_ISA_Zbkb : boolean := true; -- implement bit-manipulation instructions for cryptography
RISCV_ISA_Zbkc : boolean := true; -- implement carry-less multiplication instructions
RISCV_ISA_Zbkx : boolean := true; -- implement cryptography crossbar permutation extension
RISCV_ISA_Zbs : boolean := true; -- implement single-bit bit-manipulation extension
RISCV_ISA_Zfinx : boolean := true; -- implement 32-bit floating-point extension
RISCV_ISA_Zicntr : boolean := true; -- implement base counters
RISCV_ISA_Zicond : boolean := true; -- implement integer conditional operations
RISCV_ISA_Zihpm : boolean := true; -- implement hardware performance monitors
RISCV_ISA_Zknd : boolean := true; -- implement cryptography NIST AES decryption extension
RISCV_ISA_Zkne : boolean := true; -- implement cryptography NIST AES encryption extension
RISCV_ISA_Zknh : boolean := true; -- implement cryptography NIST hash extension
RISCV_ISA_Zksed : boolean := true; -- implement ShangMi block cypher extension
RISCV_ISA_Zksh : boolean := true; -- implement ShangMi hash extension
RISCV_ISA_Zmmul : boolean := true; -- implement multiply-only M sub-extension
RISCV_ISA_Zxcfu : boolean := true; -- implement custom (instr.) functions unit
CPU_CLOCK_GATING_EN : boolean := true; -- enable clock gating when in sleep mode
CPU_FAST_MUL_EN : boolean := true; -- use DSPs for M extension's multiplier
CPU_FAST_SHIFT_EN : boolean := true; -- use barrel shifter for shift operations
CPU_REGFILE_HW_RST : boolean := true; -- implement full hardware reset for register file
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 32*1024; -- size of processor-internal instruction memory in bytes (use a power of 2)
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes (use a power of 2)
ICACHE_EN : boolean := true; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 64; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32; -- i-cache: block size in bytes (min 4), has to be a power of 2
DCACHE_EN : boolean := true; -- implement data cache
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 32; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32; -- d-cache: block size in bytes (min 4), has to be a power of 2
-- external memory A --
EXT_MEM_A_EN : boolean := false; -- enable memory
EXT_MEM_A_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address, has to be word-aligned
EXT_MEM_A_SIZE : natural := 64; -- memory size in bytes, min 4
EXT_MEM_A_FILE : string := ""; -- memory initialization file (plain HEX), no initialization if empty
EXT_MEM_A_EN : boolean := false; -- enable memory
EXT_MEM_A_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address, has to be word-aligned
EXT_MEM_A_SIZE : natural := 64; -- memory size in bytes, min 4
EXT_MEM_A_FILE : string := ""; -- memory initialization file (plain HEX), no initialization if empty
-- external memory B --
EXT_MEM_B_EN : boolean := false; -- enable memory
EXT_MEM_B_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address, has to be word-aligned
EXT_MEM_B_SIZE : natural := 64; -- memory size in bytes, min 4
EXT_MEM_B_FILE : string := "" -- memory initialization file (plain HEX), no initialization if empty
EXT_MEM_B_EN : boolean := false; -- enable memory
EXT_MEM_B_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address, has to be word-aligned
EXT_MEM_B_SIZE : natural := 64; -- memory size in bytes, min 4
EXT_MEM_B_FILE : string := "" -- memory initialization file (plain HEX), no initialization if empty
);
end neorv32_tb;
@ -142,10 +143,10 @@ begin
RISCV_ISA_Zmmul => RISCV_ISA_Zmmul,
RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu,
-- Extension Options --
CLOCK_GATING_EN => true,
FAST_MUL_EN => FAST_MUL_EN,
FAST_SHIFT_EN => FAST_SHIFT_EN,
REGFILE_HW_RST => REGFILE_HW_RST,
CPU_CLOCK_GATING_EN => CPU_CLOCK_GATING_EN,
CPU_FAST_MUL_EN => CPU_FAST_MUL_EN,
CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN,
CPU_REGFILE_HW_RST => CPU_REGFILE_HW_RST,
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS => 5,
PMP_MIN_GRANULARITY => 4,