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🐛 fix fence signal pass-through in caches

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stnolting 2024-02-10 07:06:02 +01:00
parent 83bfb56b49
commit 72044a0b6d
4 changed files with 19 additions and 16 deletions
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1
rtl/core/neorv32_dcache.vhd
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@ -187,6 +187,7 @@ begin
bus_req_o.priv <= cpu_req_i.priv;
bus_req_o.rvso <= cpu_req_i.rvso;
bus_req_o.stb <= '0';
bus_req_o.fence <= cpu_req_i.fence;
-- fsm --
case ctrl.state is

1
rtl/core/neorv32_icache.vhd
View file

@ -189,6 +189,7 @@ begin
bus_req_o.rw <= '0'; -- read-only
bus_req_o.stb <= '0';
bus_req_o.rvso <= cpu_req_i.rvso;
bus_req_o.fence <= cpu_req_i.fence;
-- fsm --
case ctrl.state is

2
rtl/core/neorv32_package.vhd
View file

@ -56,7 +56,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090407"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090408"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

31
rtl/core/neorv32_xip.vhd
View file

@ -808,27 +808,28 @@ begin
ctrl_engine_fsm_comb: process(state, addr_reg, cache, clear_i, cpu_req_i, bus_rsp_i)
begin
-- control defaults --
state_nxt <= state;
addr_reg_nxt <= addr_reg;
state_nxt <= state;
addr_reg_nxt <= addr_reg;
-- cache defaults --
cache.ctrl_en <= '0';
cache.ctrl_we <= '0';
cache.ctrl_en <= '0';
cache.ctrl_we <= '0';
-- host response defaults --
cpu_rsp_o.ack <= '0';
cpu_rsp_o.err <= '0';
cpu_rsp_o.data <= (others => '0');
cpu_rsp_o.ack <= '0';
cpu_rsp_o.err <= '0';
cpu_rsp_o.data <= (others => '0');
-- bus interface defaults --
bus_req_o.data <= (others => '0');
bus_req_o.ben <= (others => '0');
bus_req_o.src <= cpu_req_i.src;
bus_req_o.priv <= cpu_req_i.priv;
bus_req_o.addr <= addr_reg;
bus_req_o.rw <= '0'; -- read-only
bus_req_o.stb <= '0';
bus_req_o.rvso <= cpu_req_i.rvso;
bus_req_o.data <= (others => '0');
bus_req_o.ben <= (others => '0');
bus_req_o.src <= cpu_req_i.src;
bus_req_o.priv <= cpu_req_i.priv;
bus_req_o.addr <= addr_reg;
bus_req_o.rw <= '0'; -- read-only
bus_req_o.stb <= '0';
bus_req_o.rvso <= cpu_req_i.rvso;
bus_req_o.fence <= cpu_req_i.fence;
-- fsm --
case state is