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[rtl] fix IPB size

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when having a (large) cache a large instruction prefetch buffer is not needed at all
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stnolting 2022-07-19 12:58:17 +02:00
parent cb6c842bf4
commit 722ab46f0a
1 changed files with 1 additions and 1 deletions
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rtl/system_integration/neorv32_litex_core_complex.vhd
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@ -143,7 +143,7 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
riscv_zicntr => ( false, false, true, true ), -- RISC-V standard CPU counters 'Zicntr'
riscv_zihpm => ( false, false, false, true ), -- RISC-V hardware performance monitors 'Zihpm'
fast_ops => ( false, false, true, true ), -- use DSPs and barrel-shifters
ipb => ( 2, 2, 4, 8 ), -- instruction prefetch buffer depth, power of two, min 2
ipb => ( 2, 2, 4, 4 ), -- instruction prefetch buffer depth, power of two, min 2
pmp_nr => ( 0, 0, 0, 8 ), -- number of PMP regions (0..16)
hpm_nr => ( 0, 0, 0, 8 ), -- number of HPM counters (0..29)
icache_en => ( false, false, true, true ), -- instruction cache enabled