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[docs] removed numerically-controlled oscillator (NCO) IO module

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stnolting 2021-06-27 14:53:02 +02:00
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1
CHANGELOG.md
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@ -24,6 +24,7 @@ defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/
| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 27.06.2021 | 1.5.7.5 | :warning: removed numerically-controlled oscillator (NCO, `neorv32_nco.vhd`) module as it appears to be an over-engineered clock-generator without many use cases (if you really need this module, you can wrap it within the custom functions subsystem CFS) |
| 27.06.2021 | 1.5.7.4 | :warning: removed top's fast IRQ (FIRQ) inputs `soc_firq_i`: the FIRQs are reserved for processor-internal usage only, use the `mext_irq_i` RISC-V external interrupt signal for all external interrupt applications (via dedicated interrupt conttoller), a follow-up version of the project will introduce a customizable external interrupt controller; sourced-out FIFOs into new HDL component `neorv32_fifo.vhd` |
| 26.06.2021 | 1.5.7.3 | edit of v1.5.7.2: RISC-V spec claims to leave destination registers of trapping load operation unchanged (do _not_ set to zero); minor CPU control logic optimizations; :sparkles: reworked bootloader to provide several new configuration and customization options |
| 25.06.2021 | 1.5.7.2 | optimized instruction execution FSM: less hardware utilization, :lock: now _ensures_ to write ZERO to destination register if there is an exception during a load operation; made default bootloader even more HW configuration independent (GPIO, SPI and MTIME are optional; UART is optional but highly recommended); |

3
README.md
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@ -122,7 +122,6 @@ for tightly-coupled custom co-processor extensions
**Advanced**
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
* numerically-controlled oscillator ([NCO](https://stnolting.github.io/neorv32/#_numerically_controlled_oscillator_nco))
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - implementing
the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
and compatible with the *OpenOCD* and *gdb*
@ -329,7 +328,7 @@ This overview provides some *quick links* to the most important sections of the
### :copyright: Legal
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, proprietary notice, ...
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information (_DOI_)
* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint (:de:)
[[back to top](#The-NEORV32-RISC-V-Processor)]

4
docs/datasheet/overview.adoc
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@ -119,7 +119,7 @@ RISC-V compatibility, _customization_ and _ease of use_. See the <<_project_key_
* **NEORV32 Processor (SoC)**: highly-configurable full-scale microcontroller-like processor system
** based on the NEORV32 CPU
** optional serial interfaces (UARTs, TWI, SPI)
** optional timers and counters (WDT, MTIME, NCO)
** optional timers and counters (WDT, MTIME)
** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
** optional embedded memories / caches for data, instructions and bootloader
** optional external memory interface for custom connectivity (Wishbone or AXI4-Lite)
@ -220,7 +220,6 @@ neorv32_top.vhd - NEORV32 Processor top entity
├neorv32_imem.vhd - Processor-internal instruction memory
│└neor32_application_image.vhd - IMEM application initialization image
├neorv32_mtime.vhd - Machine system timer
├neorv32_nco.vhd - Numerically-controlled oscillator
├neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface
├neorv32_pwm.vhd - Pulse-width modulation controller
├neorv32_spi.vhd - Serial peripheral interface controller
@ -294,7 +293,6 @@ between entity boundaries, so the actual utilization results might vary a bit.
| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 220 | 154 | 8192 | 0
| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0
| MTIME | Machine system timer | 289 | 200 | 0 | 0
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0
| PWM | Pulse_width modulation controller (4 channels) | 71 | 69 | 0 | 0
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0

17
docs/datasheet/soc.adoc
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@ -22,7 +22,6 @@ image::neorv32_processor.png[align=center]
* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
* _optional_ numerically-controlled oscillator (<<_numerically_controlled_oscillator_nco,**NCO**>>) with 3 independent channels
* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
@ -94,8 +93,6 @@ A wrapper for the NEORV32 Processor setup providing resolved port signals can be
| `cfs_out_o` | 32 | out | custom CFS output signal conduit
4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
| `pwm_o` | 4 | out | pulse-width modulated channels
4+^| **Numerically-Controller Oscillator (<<_numerically_controlled_oscillator_nco,NCO>>)**
| `nco_o` | 3 | out | NCO output channels
4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
| `neoled_o` | 1 | out | asynchronous serial data output
4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
@ -743,18 +740,6 @@ functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for
|======
:sectnums!:
===== _IO_NCO_EN_
[cols="4,4,2"]
[frame="all",grid="none"]
|======
| **IO_NCO_EN** | _boolean_ | true
3+| Implement numerically-controlled oscillator (NCO) when _true_.
See section <<_numerically_controlled_oscillator_nco>> for more information.
|======
:sectnums!:
===== _IO_NEOLED_EN_
@ -1168,8 +1153,6 @@ include::soc_trng.adoc[]
include::soc_cfs.adoc[]
include::soc_nco.adoc[]
include::soc_neoled.adoc[]
include::soc_sysinfo.adoc[]

129
docs/datasheet/soc_nco.adoc
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@ -1,129 +0,0 @@
<<<
:sectnums:
==== Numerically-Controlled Oscillator (NCO)
[cols="<3,<3,<4"]
[frame="topbot",grid="none"]
|=======================
| Hardware source file(s): | neorv32_nco.vhd |
| Software driver file(s): | neorv32_nco.c |
| | neorv32_nco.h |
| Top entity port: | `nco_o` | NCO output (3x 1-bit channels)
| Configuration generics: | _IO_NCO_EN_ | implement NCO when _true_
| CPU interrupts: | none |
|=======================
**Theory of Operation**
The numerically-controller oscillator (NCO) provides a precise arbitrary linear frequency generator with
three independent channels. Based on a **direct digital synthesis** core, the NCO features a 20-bit wide
accumulator that is incremented with a programmable "tuning word". Whenever the accumulator overflows, a
flip flop is toggled that provides the actual frequency output. The accumulator increment is driven by one of
eight configurable clock sources, which are derived from the processor's main clock.
The NCO features four accessible registers: the control register _NCO_CT_ and three _NCO_TUNE_CHi_ registers for
the tuning word of each channel i. The NCO is globally enabled by setting the _NCO_CT_EN_ bit in the control
register. If this bit is cleared, the accumulators of all channels are reset. The clock source for each channel i is
selected via the three bits _NCO_CT_CHi_PRSCx_ prescaler. The resulting clock is generated from the main
processor clock (f~main~) divided y the selected prescaler.
.NCO prescaler configuration
[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
[options="header",grid="rows"]
|=======================
| **`NCO_CT_CHi_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
|=======================
The resulting output frequency of each channel i is defined by the following equation:
_**f~NCO~(i)**_ = ( _f~main~[Hz]_ / `clock_prescaler`(i) ) * (`tuning_word`(i) / 2*2^20+1^)
The maximum NCO frequency f~NCOmax~ is configured when using the minimal clock prescaler and a maximum all-one
tuning word:
_**f~NCOmax~**_ = ( _f~main~[Hz]_ / 2 ) * (1 / 2*2^20+1^)
The minimum "frequency" is always 0 Hz when the tuning word is zero. The frequency resolution f~NCOres~ is
defined using the maximum clock prescaler and a minimal non-zero tuning word (= 1):
_**f~NCOres~**_ = ( _f~main~[Hz]_ / 4096 ) * (1 / 2*2^20+1^)
Assuming a processor frequency of f~main~ = 100 MHz the maximum NCO output frequency is f~NCOmax~ = 12.499
MHz with an NCO frequency resolution of f~NCOres~ = 0.00582 Hz.
**Advanced Configuration**
The idle polarity of each channel is configured via the _NCO_CT_CHi_IDLE_POL_ flag and can be either `0`
(idle low) or `1` (idle high), which basically allows to invert the NCO output. If the NCO is globally disabled
by clearing the _NCO_CT_EN_ flag, `nco_o(i)` output bit i is set to the according _NCO_CT_CHi_IDLE_POL_.
The current state of each NCO channel output can be read by software via the NCO_CT_CHi_OUTPUT bit.
The NCO frequency output is normally available via the top nco_o output signal. The according channel
output can be permanently set to zero by clearing the according NCO_CT_CHi_OE bit.
Each NCO channel can operate either in standard mode or in pulse mode. The mode is configured via the
according channel's NCO_CT_CHi_MODE control register bit.
**_Standard_ Operation Mode**
If this _NCO_CT_CHi_MODE_ bit of channel i is cleared, the channel operates in standard mode providing a
frequency with **exactly 50% duty cycle** (T~high~ = T~low~).
**_Pulse_ Operation Mode**
If the _NCO_CT_CHi_MODE_ bit of channel i is set, the channel operates in pulse mode. In this mode, the duty
cycle can be modified to generate active pulses with variable length. Note that the "active" pulse polarity is defined
by the inverted _NCO_CT_CHi_IDLE_POL_ bit.
Eight different pulse lengths are available. The active pulse length is defined as number of NCO clock
cycles, where the NCO clock is defined via the clock prescaler bits _NCO_CT_Chi_PRSCx_. The pulse length
of channel i is programmed by the 3-bit _NCO_CT_CHi_PULSEx_ configuration:
.NCO pulse length configuration
[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
[options="header",grid="rows"]
|=======================
| **`NCO_CT_CHi_PULSEx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
| Pulse length (in NCO clock cycles) | 2 | 4 | 8 | 16 | 32 | 64 | 128 | 256
|=======================
If _NCO_CT_CHi_IDLE_POL_ is cleared, T~high~ is defined by the _NCO_CT_CHi_PULSEx_ configuration and T~low~ =
T – T~high~. _If NCO_CT_CHi_IDLE_POL_ is set, T~low~ is defined by the _NCO_CT_CHi_PULSEx_ configuration and
T~high~ = T – T~low~.
The actual output frequency of the channel (defined via the clock prescaler and the tuning word) is not
affected by the pulse configuration.
For simple PWM applications, that do not require a precise frequency but a more flexible duty cycle
configuration, see section <<_pulse_width_modulation_controller_pwm>>.
<<<
.NCO register map
[cols="<4,<3,<9,^2,<11"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.22+<| `0xffffffc0` .22+<| _NCO_CT_ ^|`0` _NCO_CT_EN_ ^| r/w <| NCO enable
3+^| Channel 0 `nco_o(0)`
^|`1` _NCO_CT_CH0_MODE_ ^| r/w <| output mode (`0`=fixed 50% duty cycle; `1`=pulse mode)
^|`2` _NCO_CT_CH0_IDLE_POL_ ^| r/w <| output idle polarity
^|`3` _NCO_CT_CH0_OE_ ^| r/w <| enable output to `nco_o(0)`
^|`4` _NCO_CT_CH0_OUTPUT_ ^| r/- <| current state of `nco_o(0)`
^|`7:5` _NCO_CT_CH0_PRSC02_ : _NCO_CT_CH0_PRSC0_ ^| r/w <| 3-bit clock prescaler select
^|`10_:8` _NCO_CT_CH0_PULSE2_ : _NCO_CT_CH0_PULSE0_ ^| r/w <| 3-bit pulse length select
3+^| Channel 1 `nco_o(1)`
^|`11` _NCO_CT_CH1_MODE_ ^| r/w <| output mode (`0`=fixed 50% duty cycle; `1`=pulse mode)
^|`12` _NCO_CT_CH1_IDLE_POL_ ^| r/w <| output idle polarity
^|`13` _NCO_CT_CH1_OE_ ^| r/w <| enable output to `nco_o(1)`
^|`14` _NCO_CT_CH1_OUTPUT_ ^| r/- <| current state of `nco_o(1)`
^|`17:15` _NCO_CT_CH1_PRSC2_ : _NCO_CT_CH1_PRSC0_ ^| r/w <| 3-bit clock prescaler select
^|`20:18` _NCO_CT_CH1_PULSE2_ : _NCO_CT_CH1_PULSE0_ ^| r/w <| 3-bit pulse length select
3+^| Channel 2 `nco_o(2)`
^|`21` _NCO_CT_CH2_MODE_ ^| r/w <| output mode (`0`=fixed 50% duty cycle; `1`=pulse mode)
^|`22` _NCO_CT_CH2_IDLE_POL_ ^| r/w <| output idle polarity
^|`23` _NCO_CT_CH2_OE_ ^| r/w <| enable output to `nco_o(2)`
^|`24` _NCO_CT_CH2_OUTPUT_ ^| r/- <| current state of `nco_o(2)`
^|`27:25` _NCO_CT_CH2_PRSC2_ : _NCO_CT_CH2_PRSC0_ ^| r/w <| 3-bit clock prescaler select
^|`30:28` _NCO_CT_CH2_PULSE2_ : _NCO_CT_CH2_PULSE0_ ^| r/w <| 3-bit pulse length select
|=======================

2
docs/datasheet/soc_neoled.adoc
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@ -167,7 +167,7 @@ command).
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.22+<| `0xffffffd8` .22+<| _NEOLED_CT_ <|`0` _NEOLED_CT_EN_ ^| r/w <| NCO enable
.22+<| `0xffffffd8` .22+<| _NEOLED_CT_ <|`0` _NEOLED_CT_EN_ ^| r/w <| NEOLED enable
<|`1` _NEOLED_CT_MODE_ ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit
<|`2` _NEOLED_CT_BSCON_ ^| r/w <| busy flag / IRQ trigger configuration (see table above)
<|`3` _NEOLED_CT_PRSC0_ ^| r/w <| 3-bit clock prescaler, bit 0

1
docs/datasheet/soc_sysinfo.adoc
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@ -60,7 +60,6 @@ and default clock speed) for correct operation.
| `22` | _SYSINFO_FEATURES_IO_WDT_ | set if the WDT is implemented (via top's _IO_WDT_EN_ generic)
| `23` | _SYSINFO_FEATURES_IO_CFS_ | set if the custom functions subsystem is implemented (via top's _IO_CFS_EN_ generic)
| `24` | _SYSINFO_FEATURES_IO_TRNG_ | set if the TRNG is implemented (via top's _IO_TRNG_EN_ generic)
| `25` | _SYSINFO_FEATURES_IO_NCO_ | set if the NCO is implemented (via top's _IO_NCO_EN_ generic)
| `26` | _SYSINFO_FEATURES_IO_UART1_ | set if the secondary UART1 is implemented (via top's _IO_UART1_EN_ generic)
| `27` | _SYSINFO_FEATURES_IO_NEOLED_ | set if the NEOLED is implemented (via top's _IO_NEOLED_EN_ generic)
|=======================

1
docs/datasheet/software.adoc
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@ -66,7 +66,6 @@ files are currently part of the NEORV32 core library:
| `neorv32_gpio.c` | `neorv32_gpio.h` | HW driver functions for the **GPIO**
| - | `neorv32_intrinsics.h` | macros for custom intrinsics/instructions
| `neorv32_mtime.c` | `neorv32_mtime.h` | HW driver functions for the **MTIME**
| `neorv32_nco.c` | `neorv32_nco.h` | HW driver functions for the **NCO**
| `neorv32_neoled.c` | `neorv32_neoled.h` | HW driver functions for the **NEOLED**
| `neorv32_pwm.c` | `neorv32_pwm.h` | HW driver functions for the **PWM**
| `neorv32_rte.c` | `neorv32_rte.h` | NEORV32 **runtime environment** and helpers

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