mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-24 14:17:51 -04:00
Merge pull request #291 from stnolting/cleanup_riscv_arch_test
Move riscv-arch-test tests into separate repository
This commit is contained in:
stnolting
GitHub
commit
76d97e120a
28 changed files with 7 additions and 669 deletions
36
.github/workflows/riscv-arch-test.yml
vendored
36
.github/workflows/riscv-arch-test.yml
vendored
|
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@ -1,36 +0,0 @@
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# Run the RISC-V riscv-arch-test test framework port to check current NEORV32 version
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name: 'riscv-arch-test'
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on:
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workflow_dispatch:
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jobs:
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build:
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runs-on: ubuntu-latest
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strategy:
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fail-fast: false
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matrix:
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suite:
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- I
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- C
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- M
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- privilege
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- Zifencei
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name: 'RISC-V Compatibility Check'
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steps:
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- name: '🧰 Repository Checkout'
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uses: actions/checkout@v2
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- name: '⚙️ Setup Software Framework'
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uses: docker://ghcr.io/stnolting/neorv32/sim
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with:
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args: ./do.py BuildAndInstallSoftwareFrameworkTests
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- name: '🚧 Run RISC-V Architecture Tests'
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uses: docker://ghcr.io/stnolting/neorv32/sim
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with:
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args: ./do.py RunRISCVArchitectureTests -s ${{ matrix.suite }}
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2
.gitignore
vendored
2
.gitignore
vendored
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@ -34,6 +34,4 @@ sw/image_gen/image_gen.exe
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*.cf
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*.o
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# riscv-arch-test
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/sim/work/
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|
|
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4
.gitmodules
vendored
4
.gitmodules
vendored
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@ -1,4 +0,0 @@
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[submodule "riscv-arch-test/work/riscv-arch-test"]
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path = sw/isa-test/riscv-arch-test
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url = https://github.com/riscv-non-isa/riscv-arch-test.git
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ignore = dirty
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@ -73,10 +73,10 @@ setting up your NEORV32 setup!
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[](https://stnolting.github.io/neorv32)
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\
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32-verif/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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The processor passes the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test) and can
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The processor passes the [official RISC-V architecture tests](https://github.com/riscv-non-isa/riscv-arch-test) and can
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run any C programs (for example from the [`sw/example`](https://github.com/stnolting/neorv32/tree/main/sw/example)
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folder). The SoC can be synthesized for _any_ target technology - tested on Intel, Xilinx and Lattice FPGAs.
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|
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29
do.py
29
do.py
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@ -33,35 +33,6 @@ def task_BuildAndInstallSoftwareFrameworkTests():
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}
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def task_RunRISCVArchitectureTests():
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return {
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"actions": [CmdAction(
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"./run_riscv_arch_test.sh {suite}",
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cwd=ROOT / "sim"
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)],
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"doc": "Run RISC-V Architecture Tests",
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"params": [
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{
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"name": "suite",
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"short": "s",
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"long": "suite",
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"default": "M",
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"choices": ((item, "") for item in [
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"I",
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"C",
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"M",
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"privilege",
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"Zifencei",
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"rv32e_C",
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"rv32e_E",
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"rv32e_M"
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]),
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"help": "Test suite to be executed",
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}
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],
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}
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def task_Documentation():
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return {
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"actions": ["make -C docs {posargs}"],
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|
|
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@ -125,13 +125,10 @@ memory operations).
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:sectnums:
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=== RISC-V Compatibility
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The NEORV32 CPU passes the rv32_m/I, rv32_m/M, rv32_m/C, rv32_m/privilege, and
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rv32_m/Zifencei tests of the official RISC-V Architecture Tests (GitHub). The port files for the
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NEORV32 processor are located in the repository's `sw/isa-test` folder.
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[NOTE]
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See section https://stnolting.github.io/neorv32/ug/#_risc_v_architecture_test_framework[User Guide: RISC-V Architecture Test Framework]
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for information how to run the tests on the NEORV32.
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The NEORV32 CPU passes the tests of the _RISC-V Architecture Test Framework_. This framework is used to check
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RISC-V implementations for compatibility with the official RISC-V ISA specifications.
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The NEORV32 port of this test framework has been moved to a separate repository:
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https://github.com/stnolting/neorv32-verif
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.**RISC-V `rv32_m/C` Tests**
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...................................
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|
|
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@ -139,10 +139,7 @@ neorv32 - Project home folder
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├lib - Processor core library
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│├include - Header files (*.h)
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│└source - Source files (*.c)
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├image_gen - Helper program to generate NEORV32 executables
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├isa-test
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│├riscv-arch-test - RISC-V spec. compatibility test framework (submodule)
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│└port-neorv32 - Port files for the official RISC-V architecture tests
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├image_gen - Helper program to generate NEORV32 executables^
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├ocd_firmware - Source code for on-chip debugger's "park loop"
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├openocd - OpenOCD on-chip debugger configuration files
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└svd - Processor system view description file (CMSIS-SVD)
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|
|
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@ -48,8 +48,6 @@ include::zephyr_support.adoc[]
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include::free_rtos_support.adoc[]
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include::riscv_architecture_tests.adoc[]
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include::debugging_with_ocd.adoc[]
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|
|
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@ -1,12 +0,0 @@
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<<<
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:sectnums:
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== RISC-V Architecture Test Framework
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The NEORV32 Processor passes the according tests provided by the official RISC-V Architecture Test Suite
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(V2.0+), which is available online at GitHub: https://github.com/riscv/riscv-arch-test
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All files required for executing the test framework on a simulated instance of the processor (including port
|
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files) are located in the `sw/isa-test` folder of the NEORV32 repository. The test framework is executed via the
|
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`sim/run_riscv_arch_test.sh` script. Take a look at the provided `sim/README.md`
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(https://github.com/stnolting/neorv32/tree/main/sim[online at GitHub])
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file for more information on how to run the tests and how testing is conducted in detail.
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@ -22,37 +22,3 @@ VUnit testbench for the NEORV32 Processor.
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- [`neorv32_tb.vhd`](neorv32_tb.vhd)
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- [`uart_rx_pkg.vhd`](uart_rx_pkg.vhd)
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- [`uart_rx.vhd`](uart_rx.vhd)
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## [`run_riscv_arch_test.sh`](run_riscv_arch_test.sh): NEORV32 RISC-V Architecture Test Framework
|
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This script tests the NEORV32 Processor for RISC-V compatibility using the
|
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[official RISC-V architecture test suite v2+](https://github.com/riscv/riscv-arch-test).
|
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The core's HDL sources are *simulated* using `GHDL` to provide a virtual execution platform for the test framework:
|
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|
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* `rv32i_m/C` - compressed instructions
|
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* `rv32i_m/I` - base ISA
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* `rv32i_m/M` - hardware integer multiplication and division
|
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* `rv32i_m/privilege` - privileged architecture
|
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* `rv32i_m/Zifencei` - instruction stream synchronization (for example for self-modifying code)
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:warning: The RISC-V GCC toolchain (`riscv{32|64}-unknown-elf`) is required for program compilation, and the simulation
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depends on `simple/ghdl_sim.sh`.
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To execute all the supported tests open a terminal and run [`./sim/run_riscv_arch_test.sh`](run_riscv_arch_test.sh),
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which does the following:
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* Make a local copy of the NEORV32 `rtl` folder in `work/`, to keep the project's core files clean.
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* Clone (as `git submodule`) the [riscv-arch-test repository](https://github.com/riscv/riscv-arch-test) into `sw/isa-test/riscv-arch-test`.
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* Install (copy) the custom `neorv32` test target from `sw/isa-test/port-neorv32` to the
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test suite's target folder `work/riscv-arch-test/riscv-target/neorv32`.
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* Run the actual tests.
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:warning: Simulating all the test cases takes quite some time. Some tests use an optimised description of IMEM
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(`neorv32_imem.simple.vhd`), but others require the original because they execute self-modifying code.
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:warning: If the simulation of a test does not generate any signature output at all or if the signature is truncated,
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try increasing the simulation time by modiying the `SIM_TIME` variable when calling the test makefiles in `run_riscv_arch_test.sh`.
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More datails regarding the actual simulation process can be found in the
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[target's `README`](../sw/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md).
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|
|
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@ -1,108 +0,0 @@
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#!/usr/bin/env bash
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# Abort if any command returns != 0
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set -e
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cd $(dirname "$0")
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header() {
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echo "--------------------------------------------------------------------------"
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echo "> $@..."
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echo "--------------------------------------------------------------------------"
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}
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RISCV_PREFIX="${RISCV_PREFIX:-riscv32-unknown-elf-}"
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header "Checking RISC-V GCC toolchain"
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"$RISCV_PREFIX"gcc -v
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header "Checking 'riscv-arch-test' GitHub repository (submodule)"
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git submodule update --init
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header "Copying neorv32 test-target into riscv-arch-test framework"
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(
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cd ../sw/isa-test
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target_device='riscv-arch-test/riscv-target/neorv32'
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if [ -d "$target_device" ]; then rm -rf "$target_device"; fi
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cp -vr port-neorv32 "$target_device"
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cp -f port-neorv32/riscv-test-suite/rv32i_m/C/references/* riscv-arch-test/riscv-test-suite/rv32i_m/C/references
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cp -f port-neorv32/riscv-test-suite/rv32i_m/privilege/references/* riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references
|
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)
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header "Making local copy of NEORV32 'rtl' and 'sim' folders"
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export NEORV32_LOCAL_RTL=${NEORV32_LOCAL_RTL:-$(pwd)/work}
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rm -rf "$NEORV32_LOCAL_RTL"
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cp -r ../rtl "$NEORV32_LOCAL_RTL"
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rm -f $NEORV32_LOCAL_RTL/core/mem/*.legacy.vhd
|
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|
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header "Starting RISC-V architecture tests"
|
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|
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./simple/ghdl.setup.sh
|
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|
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# work in progress FIXME
|
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printf "\n\e[1;33m[WARNING] 'I/jal-01' test is currently disabled (GHDL simulation issue)! \e[0m\n\n"
|
||||
printf "\n\e[1;33m[WARNING] Overwriting default 'C/cebreak' and 'privilege/ebreak' test references! \e[0m\n\n"
|
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sleep 4
|
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|
||||
|
||||
makeArgs="-C $(pwd)/../sw/isa-test/riscv-arch-test NEORV32_ROOT=$(pwd)/.. XLEN=32 RISCV_TARGET=neorv32"
|
||||
makeTargets='clean build run verify'
|
||||
|
||||
[ -n "$1" ] && SUITES="$@" || SUITES='I C M privilege Zifencei'
|
||||
|
||||
for suite in $SUITES; do
|
||||
case "$suite" in
|
||||
I) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I clean build;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='add-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='addi-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='and-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='andi-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='auipc-01' run;
|
||||
make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I RISCV_TEST='beq-01' run;
|
||||
make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I RISCV_TEST='bge-01' run;
|
||||
make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I RISCV_TEST='bgeu-01' run;
|
||||
make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I RISCV_TEST='blt-01' run;
|
||||
make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I RISCV_TEST='bltu-01' run;
|
||||
make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I RISCV_TEST='bne-01' run;
|
||||
# make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I RISCV_TEST='jal-01' run;
|
||||
make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I RISCV_TEST='jalr-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='lb-align-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='lbu-align-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='lh-align-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='lhu-align-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='lui-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='lw-align-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='or-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='ori-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='sb-align-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='sh-align-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='sll-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='slli-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='slt-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='slti-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='sltiu-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='sltu-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='sra-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='srai-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='srl-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='srli-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='sub-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='sw-align-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='xor-01' run;
|
||||
make --silent $makeArgs SIM_TIME=600us RISCV_DEVICE=I RISCV_TEST='xori-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='fence-01' run;
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=I RISCV_TEST='fence-01' verify;;
|
||||
C) make --silent $makeArgs SIM_TIME=400us RISCV_DEVICE=C $makeTargets;;
|
||||
M) make --silent $makeArgs SIM_TIME=800us RISCV_DEVICE=M $makeTargets;;
|
||||
privilege) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=privilege $makeTargets;;
|
||||
Zifencei) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT $makeTargets;;
|
||||
|
||||
rv32e_C) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/C $makeTargets;;
|
||||
rv32e_E) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/E $makeTargets;;
|
||||
rv32e_M) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/M $makeTargets;;
|
||||
esac
|
||||
done
|
||||
|
||||
printf "\nRISC-V architecture tests completed successfully"
|
||||
|
|
@ -28,12 +28,6 @@ memory initialization files (for memory-persistent applications and for the boot
|
|||
This program is automatically compiled using the native GCC when invoking one of the application compilation makefiles.
|
||||
|
||||
|
||||
## [isa-test](isa-test)
|
||||
|
||||
NEORV32 RISC-V Architecture Test Framework.
|
||||
See [sim/README](../sim/README.md).
|
||||
|
||||
|
||||
## [lib](lib)
|
||||
|
||||
Core libraries (sources and header files) and helper functions for using the processor peripherals and the CPU itself.
|
||||
|
|
|
|||
|
|
@ -1,74 +0,0 @@
|
|||
ifndef NEORV32_ROOT
|
||||
$(error NEORV32_ROOT is undefined)
|
||||
endif
|
||||
|
||||
NEORV32_LOCAL_RTL ?= $(NEORV32_ROOT)/sim/work
|
||||
|
||||
TARGET_SIM ?= ghdl
|
||||
TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
|
||||
|
||||
ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
|
||||
$(error Target simulator executable '$(TARGET_SIM)` not found)
|
||||
endif
|
||||
|
||||
NEORV32_MARCH ?= rv32i
|
||||
NEORV32_MABI ?= ilp32
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
RISCV_GCC ?= $(RISCV_PREFIX)gcc
|
||||
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
|
||||
RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
|
||||
RISCV_READELF ?= $(RISCV_PREFIX)readelf
|
||||
RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=$(NEORV32_MARCH) -mabi=$(NEORV32_MABI)
|
||||
|
||||
NEORV32_LINK ?= link.imem_rom.ld
|
||||
|
||||
COMPILE_TARGET ?= \
|
||||
$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
|
||||
$$(RISCV_TARGET_FLAGS) \
|
||||
-I$(ROOTDIR)/riscv-test-suite/env/ \
|
||||
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
|
||||
-T$(TARGETDIR)/$(RISCV_TARGET)/$(NEORV32_LINK) \
|
||||
$$(<) -o $$@
|
||||
|
||||
NEORV32_CPU_EXTENSION_RISCV_C ?= false
|
||||
NEORV32_CPU_EXTENSION_RISCV_E ?= false
|
||||
NEORV32_CPU_EXTENSION_RISCV_M ?= false
|
||||
NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI ?= false
|
||||
NEORV32_MEM_INT_IMEM_SIZE ?= '2097152'
|
||||
|
||||
NEORV32_SOFTWARE_EXAMPLE ?= $(NEORV32_ROOT)/sw/example/blink_led
|
||||
|
||||
ifeq ($(NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI), true)
|
||||
RUN_TARGET ?= \
|
||||
echo "copying/using SIM-only IMEM (pre-initialized RAM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; \
|
||||
cp -f $(NEORV32_ROOT)/sim/simple/neorv32_imem.iram.simple.vhd $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd;
|
||||
else
|
||||
RUN_TARGET ?= \
|
||||
echo "copying/using SIM-only IMEM (pre-initialized ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; \
|
||||
cp -f $(NEORV32_ROOT)/sim/simple/neorv32_imem.simple.vhd $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd;
|
||||
endif
|
||||
|
||||
RUN_TARGET += \
|
||||
cd $(work_dir_isa); \
|
||||
echo ">"; \
|
||||
rm -f $(NEORV32_ROOT)/sim/*.out; \
|
||||
make -C $(NEORV32_SOFTWARE_EXAMPLE) main.elf; \
|
||||
cp -f $< $(NEORV32_SOFTWARE_EXAMPLE)/main.elf; \
|
||||
make -C $(NEORV32_SOFTWARE_EXAMPLE) main.bin install; \
|
||||
touch $(NEORV32_ROOT)/sim/simple/neorv32.uart0.sim_mode.data.out; \
|
||||
GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_ROOT)/sim/simple/ghdl.run.sh \
|
||||
--stop-time=$(SIM_TIME) \
|
||||
-gCPU_EXTENSION_RISCV_A=false \
|
||||
-gCPU_EXTENSION_RISCV_C=$(NEORV32_CPU_EXTENSION_RISCV_C) \
|
||||
-gCPU_EXTENSION_RISCV_E=$(NEORV32_CPU_EXTENSION_RISCV_E) \
|
||||
-gCPU_EXTENSION_RISCV_M=$(NEORV32_CPU_EXTENSION_RISCV_M) \
|
||||
-gCPU_EXTENSION_RISCV_U=false \
|
||||
-gCPU_EXTENSION_RISCV_Zicsr=true \
|
||||
-gCPU_EXTENSION_RISCV_Zifencei=true \
|
||||
-gEXT_IMEM_C=false \
|
||||
-gMEM_INT_IMEM_SIZE=$(NEORV32_MEM_INT_IMEM_SIZE); \
|
||||
cp $(NEORV32_ROOT)/sim/simple/neorv32.uart0.sim_mode.data.out $(*).signature.output; \
|
||||
echo "<";
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
# NEORV32 Port for running the RISC-V Architecture Tests
|
||||
|
||||
**:warning: This folder might be _outsourced_ someday into an individual repository. Furthermore, the default
|
||||
RISC-V architecture tests will be superseded by the RISCOF test framework. I am planning to make
|
||||
a port for this new test framework.**
|
||||
|
||||
The following tasks are executed by the device makefiles:
|
||||
|
||||
* replace the original processor's IMEM rtl file by a simulation-optimized IMEM (ROM!)
|
||||
* `sed` command is used to modify the default testbench (`neorv32/sim/neorv32_tb.simple.vhd`):
|
||||
* enable/disable the required `CPU_EXTENSION_RISCV_xxx` VHDL configuration generics in the testbench (`neorv32/sim/neorv32_tb.simple.vhd`)
|
||||
* set the processor memory configuration
|
||||
* override the default frameworks reference data for `C/cebreak-01` and `privilege/ebreak` tests
|
||||
* this is required as the NEORV32 sets `mtval` CSR to zero on software breakpoints
|
||||
* compile test code and install application image to processor's `rtl/core` folder
|
||||
* compilation uses the `link.imem_rom.ld` linker script as default; code (the test code) is executed from simulation-optimized IMEM (which is read-only); data including signature is stored to DMEM
|
||||
* certain areas in the DMEM are initialized using port code in `model_test.h` (`RVTEST` = 0xbabecafe and `SIGNATURE` = 0xdeadbeef); can be disabled using `RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT`
|
||||
* the processor is simulated using the default testbench
|
||||
* the results are dumped via the SIM_MODE feature of UART0
|
||||
* the according code can be found in the `RVMODEL_HALT` macro in `model_test.h`
|
||||
* data output (the "signature") is zero-padded to be always a multiple of 16 bytes
|
||||
|
||||
|
||||
## Notes
|
||||
|
||||
:information_source: The `Zifencei` test requires the r/w/e capabilities of the original IMEM rtl file.
|
||||
Hence, the original file is restored for this test. Also, this test uses `link.imem_ram.ld` as linker script since the
|
||||
IMEM is used as RAM to allow self-modifying code.
|
||||
|
||||
:information_source: The `RVMODEL_BOOT` macro in `model_test.h` provides a simple "dummy trap handler" that just advances
|
||||
to the next instruction. This trap handler is required for some `C` tests as the NEORV32 will raise an illegal instruction
|
||||
exception for **all** unimplemented instructions. The trap handler can be overridden (by changing `mtval` CSR) if a test
|
||||
uses the default trap handler of the test framework.
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
NEORV32_MARCH ?= rv32ec
|
||||
NEORV32_MABI ?= ilp32e
|
||||
NEORV32_CPU_EXTENSION_RISCV_C ?= true
|
||||
NEORV32_CPU_EXTENSION_RISCV_E ?= true
|
||||
|
||||
include $(NEORV32_ROOT)/sw/isa-test/common.mk
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
NEORV32_MARCH ?= rv32e
|
||||
NEORV32_MABI ?= ilp32e
|
||||
NEORV32_CPU_EXTENSION_RISCV_E ?= true
|
||||
|
||||
include $(NEORV32_ROOT)/sw/isa-test/common.mk
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
NEORV32_MARCH ?= rv32em
|
||||
NEORV32_MABI ?= ilp32e
|
||||
NEORV32_CPU_EXTENSION_RISCV_E ?= true
|
||||
NEORV32_CPU_EXTENSION_RISCV_M ?= true
|
||||
|
||||
include $(NEORV32_ROOT)/sw/isa-test/common.mk
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
NEORV32_MARCH ?= rv32ic
|
||||
NEORV32_CPU_EXTENSION_RISCV_C ?= true
|
||||
|
||||
include $(NEORV32_ROOT)/sw/isa-test/common.mk
|
||||
|
|
@ -1 +0,0 @@
|
|||
include $(NEORV32_ROOT)/sw/isa-test/common.mk
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
NEORV32_MARCH ?= rv32im
|
||||
NEORV32_CPU_EXTENSION_RISCV_M ?= true
|
||||
|
||||
include $(NEORV32_ROOT)/sw/isa-test/common.mk
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
NEORV32_MARCH ?= rv32im
|
||||
NEORV32_LINK ?= link.imem_ram.ld
|
||||
NEORV32_MEM_INT_IMEM_SIZE ?= '16384'
|
||||
NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI ?= true
|
||||
|
||||
include $(NEORV32_ROOT)/sw/isa-test/common.mk
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
NEORV32_CPU_EXTENSION_RISCV_C ?= true
|
||||
|
||||
include $(NEORV32_ROOT)/sw/isa-test/common.mk
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
ENTRY(rvtest_entry_point)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
.text :
|
||||
{
|
||||
*(.text.init)
|
||||
. = ALIGN(0x1000);
|
||||
*(.text)
|
||||
. = ALIGN(0x1000);
|
||||
*(.tohost)
|
||||
*(.data)
|
||||
*(.data.string)
|
||||
*(.bss)
|
||||
. = ALIGN(0x1000);
|
||||
|
||||
_end = .;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
ENTRY(rvtest_entry_point)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
.text :
|
||||
{
|
||||
*(.text.init)
|
||||
. = ALIGN(0x1000);
|
||||
*(.text)
|
||||
. = ALIGN(0x1000);
|
||||
_end = .;
|
||||
}
|
||||
|
||||
. = 0x80000000;
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(0x1000);
|
||||
*(.tohost)
|
||||
*(.data)
|
||||
*(.data.string)
|
||||
*(.bss)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,216 +0,0 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
// Modified by Stephan Nolting for the NEORV32 Processor
|
||||
|
||||
// override CODE_REL_TVAL_MSK to avoid PC adjustment for SW breakpoints (break instructions)
|
||||
#define CODE_REL_TVAL_MSK 0xC008 << (REGWIDTH*8-16)
|
||||
|
||||
|
||||
#ifndef _COMPLIANCE_MODEL_H
|
||||
#define _COMPLIANCE_MODEL_H
|
||||
|
||||
#define RVMODEL_DATA_SECTION \
|
||||
.pushsection .tohost,"aw",@progbits; \
|
||||
.align 8; .global tohost; tohost: .dword 0; \
|
||||
.align 8; .global fromhost; fromhost: .dword 0; \
|
||||
.popsection; \
|
||||
.align 8; .global begin_regstate; begin_regstate: \
|
||||
.word 128; \
|
||||
.align 8; .global end_regstate; end_regstate: \
|
||||
.word 4;
|
||||
|
||||
//RV_COMPLIANCE_HALT
|
||||
// neorv32: this will dump the results via the UART0_SIM_MODE data file output
|
||||
// neorv32: due to the modifications on "end_signature" (not 4-aligned) we need to make sure we output a 4-aligned number of data here
|
||||
// neorv32: -> for zero-padding of the rest of the SIGNATURE section
|
||||
#define RVMODEL_HALT \
|
||||
signature_dump: \
|
||||
la a0, begin_signature; \
|
||||
la a1, end_signature; \
|
||||
li a2, 0xFFFFFFA4; \
|
||||
signature_dump_loop: \
|
||||
beq a0, a1, signature_dump_padding; \
|
||||
lw t0, 0(a0); \
|
||||
sw t0, 0(a2); \
|
||||
addi a0, a0, 4; \
|
||||
j signature_dump_loop; \
|
||||
nop; \
|
||||
nop; \
|
||||
signature_dump_padding: \
|
||||
andi a0, a1, 0x0000000C; \
|
||||
beq a0, zero, signature_dump_end; \
|
||||
li t0, 16; \
|
||||
sub a0, t0, a0; \
|
||||
signature_dump_padding_loop: \
|
||||
beq a0, zero, signature_dump_end; \
|
||||
sw zero, 0(a2); \
|
||||
addi a0, a0, -4; \
|
||||
j signature_dump_padding_loop; \
|
||||
signature_dump_end: \
|
||||
j signature_dump_end
|
||||
|
||||
//TODO: declare the start of your signature region here. Nothing else to be used here.
|
||||
// The .align 4 ensures that the signature ends at a 16-byte boundary
|
||||
#define RVMODEL_DATA_BEGIN \
|
||||
.align 4; .global begin_signature; begin_signature:
|
||||
|
||||
//TODO: declare the end of the signature region here. Add other target specific contents here.
|
||||
//neorv32: DO NOT use align_4 here! end_signature is used to indicate the actual "number" of signature words
|
||||
#define RVMODEL_DATA_END \
|
||||
.global end_signature; end_signature: \
|
||||
RVMODEL_DATA_SECTION
|
||||
|
||||
//RVMODEL_BOOT
|
||||
// neorv32: enable UART0 (ctrl(28)) and enable UART0_SIM_MODE (ctrl(12))
|
||||
// neorv32: initialize the complete RVTEST_DATA section in data RAM (DMEM) with 0xBABECAFE
|
||||
// neorv32: initialize the complete SIGNATURE section (that is a multiple of four 32-bit entries) in data RAM (DMEM) with 0xDEADBEEF
|
||||
// neorv32: this code also provides a dummy trap handler that just moves on to the next instruction
|
||||
// neorv32: -> this trap handler can be overridden by the compliance-suite by modifying mtval
|
||||
// neorv32: -> the dummy trap handler is required to deal with the neorv32 X extension (-> all illegal/undefined instruction trigger an exception)
|
||||
#ifdef NEORV32_NO_DATA_INIT
|
||||
// ------------------------- WITHOUT DATA INIT -------------------------
|
||||
#define RVMODEL_BOOT \
|
||||
core_init: \
|
||||
la x1, core_dummy_trap_handler; \
|
||||
csrw mtvec, x1; \
|
||||
csrw mie, x0; \
|
||||
j uart0_sim_mode_init; \
|
||||
nop; \
|
||||
nop; \
|
||||
.balign 4; \
|
||||
core_dummy_trap_handler: \
|
||||
csrw mscratch, sp; \
|
||||
la sp, end_signature; \
|
||||
addi sp, sp, 32; \
|
||||
sw x8, 0(sp); \
|
||||
sw x9, 4(sp); \
|
||||
csrr x8, mcause; \
|
||||
blt x8, zero, core_dummy_trap_handler_irq; \
|
||||
csrr x8, mepc; \
|
||||
core_dummy_trap_handler_exc_c_check: \
|
||||
lh x9, 0(x8); \
|
||||
andi x9, x9, 3; \
|
||||
addi x8, x8, +2; \
|
||||
csrw mepc, x8; \
|
||||
addi x8, zero, 3; \
|
||||
bne x8, x9, core_dummy_trap_handler_irq; \
|
||||
core_dummy_trap_handler_exc_uncrompressed: \
|
||||
csrr x8, mepc; \
|
||||
addi x8, x8, +2; \
|
||||
csrw mepc, x8; \
|
||||
core_dummy_trap_handler_irq: \
|
||||
lw x9, 0(sp); \
|
||||
lw x8, 4(sp); \
|
||||
csrr sp, mscratch; \
|
||||
mret; \
|
||||
nop; \
|
||||
nop; \
|
||||
uart0_sim_mode_init: \
|
||||
li a0, 0xFFFFFFA0; \
|
||||
sw zero, 0(a0); \
|
||||
li a1, 1 << 28; \
|
||||
li a2, 1 << 12; \
|
||||
or a1, a1, a2; \
|
||||
sw a1, 0(a0);
|
||||
|
||||
#else
|
||||
|
||||
// ------------------------- WITH DATA INIT -------------------------
|
||||
#define RVMODEL_BOOT \
|
||||
core_init: \
|
||||
la x1, core_dummy_trap_handler; \
|
||||
csrw mtvec, x1; \
|
||||
csrw mie, x0; \
|
||||
nop; \
|
||||
nop; \
|
||||
init_rvtest_data: \
|
||||
la a0, rvtest_data_begin; \
|
||||
la a1, rvtest_data_end; \
|
||||
li a2, 0xBABECAFE; \
|
||||
init_rvtest_data_loop: \
|
||||
beq a0, a1, init_rvtest_data_loop_end; \
|
||||
sw a2, 0(a0); \
|
||||
addi a0, a0, 4; \
|
||||
j init_rvtest_data_loop; \
|
||||
init_rvtest_data_loop_end: \
|
||||
nop; \
|
||||
nop; \
|
||||
init_signature: \
|
||||
la a0, begin_signature; \
|
||||
la a1, end_signature; \
|
||||
li a2, 0xDEADBEEF; \
|
||||
init_signature_loop: \
|
||||
beq a0, a1, init_signature_loop_end; \
|
||||
sw a2, 0(a0); \
|
||||
addi a0, a0, 4; \
|
||||
j init_signature_loop; \
|
||||
init_signature_loop_end: \
|
||||
j uart0_sim_mode_init; \
|
||||
nop; \
|
||||
nop; \
|
||||
.balign 4; \
|
||||
core_dummy_trap_handler: \
|
||||
csrw mscratch, sp; \
|
||||
la sp, end_signature; \
|
||||
addi sp, sp, 32; \
|
||||
sw x8, 0(sp); \
|
||||
sw x9, 4(sp); \
|
||||
csrr x8, mcause; \
|
||||
blt x8, zero, core_dummy_trap_handler_irq; \
|
||||
csrr x8, mepc; \
|
||||
core_dummy_trap_handler_exc_c_check: \
|
||||
lh x9, 0(x8); \
|
||||
andi x9, x9, 3; \
|
||||
addi x8, x8, +2; \
|
||||
csrw mepc, x8; \
|
||||
addi x8, zero, 3; \
|
||||
bne x8, x9, core_dummy_trap_handler_irq; \
|
||||
core_dummy_trap_handler_exc_uncrompressed: \
|
||||
csrr x8, mepc; \
|
||||
addi x8, x8, +2; \
|
||||
csrw mepc, x8; \
|
||||
core_dummy_trap_handler_irq: \
|
||||
lw x9, 0(sp); \
|
||||
lw x8, 4(sp); \
|
||||
csrr sp, mscratch; \
|
||||
mret; \
|
||||
nop; \
|
||||
nop; \
|
||||
uart0_sim_mode_init: \
|
||||
li a0, 0xFFFFFFA0; \
|
||||
sw zero, 0(a0); \
|
||||
li a1, 1 << 28; \
|
||||
li a2, 1 << 12; \
|
||||
or a1, a1, a2; \
|
||||
sw a1, 0(a0);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//RVTEST_IO_INIT
|
||||
#define RVMODEL_IO_INIT
|
||||
//RVTEST_IO_WRITE_STR
|
||||
#define RVMODEL_IO_WRITE_STR(_R, _STR)
|
||||
//RVTEST_IO_CHECK
|
||||
#define RVMODEL_IO_CHECK()
|
||||
|
||||
//RVTEST_IO_ASSERT_GPR_EQ
|
||||
#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
|
||||
//RVTEST_IO_ASSERT_SFPR_EQ
|
||||
#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
|
||||
//RVTEST_IO_ASSERT_DFPR_EQ
|
||||
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
|
||||
|
||||
// TODO: specify the routine for setting machine software interrupt
|
||||
#define RVMODEL_SET_MSW_INT
|
||||
|
||||
// TODO: specify the routine for clearing machine software interrupt
|
||||
#define RVMODEL_CLEAR_MSW_INT
|
||||
|
||||
// TODO: specify the routine for clearing machine timer interrupt
|
||||
#define RVMODEL_CLEAR_MTIMER_INT
|
||||
|
||||
// TODO: specify the routine for clearing machine external interrupt
|
||||
#define RVMODEL_CLEAR_MEXT_INT
|
||||
|
||||
#endif // _COMPLIANCE_MODEL_H
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
00000000
|
||||
11111111
|
||||
0000008f
|
||||
00000003
|
||||
00000108
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
00000000
|
||||
11111111
|
||||
0000008f
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||||
00000003
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||||
00000108
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
|
|
@ -1 +0,0 @@
|
|||
Subproject commit 3916e19b47b02ce7eadedf144f6cb47501e4eb31
|
||||
Loading…
Add table
Add a link
Reference in a new issue