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[rtl] make sure FIFO size is always a power of 2
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1 changed files with 13 additions and 16 deletions
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@ -65,13 +65,16 @@ end neorv32_fifo;
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architecture neorv32_fifo_rtl of neorv32_fifo is
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-- make sure FIFO depth is a power of two --
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constant fifo_depth_c : natural := cond_sel_natural_f(is_power_of_two_f(FIFO_DEPTH), FIFO_DEPTH, 2**index_size_f(FIFO_DEPTH));
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-- FIFO --
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type fifo_data_t is array (0 to FIFO_DEPTH-1) of std_ulogic_vector(FIFO_WIDTH-1 downto 0);
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type fifo_data_t is array (0 to fifo_depth_c-1) of std_ulogic_vector(FIFO_WIDTH-1 downto 0);
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type fifo_t is record
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we : std_ulogic; -- write enable
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re : std_ulogic; -- read enable
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w_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- write pointer
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r_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- read pointer
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w_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- write pointer
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r_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- read pointer
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data : fifo_data_t; -- fifo memory
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buf : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- if single-entry FIFO
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match : std_ulogic;
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@ -84,16 +87,10 @@ architecture neorv32_fifo_rtl of neorv32_fifo is
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signal fifo : fifo_t;
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-- misc --
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signal level_diff : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0);
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signal level_diff : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0);
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert not (FIFO_DEPTH = 0) report "NEORV32 CONFIG ERROR: FIFO depth has to be > 0." severity error;
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assert not (is_power_of_two_f(FIFO_DEPTH) = false) report "NEORV32 CONFIG ERROR: FIFO depth has to be a power of two." severity error;
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fifo.re <= re_i when (FIFO_SAFE = false) else (re_i and fifo.avail); -- SAFE = read only if data available
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@ -127,7 +124,7 @@ begin
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-- FIFO Status ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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check_large:
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if (FIFO_DEPTH > 1) generate
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if (fifo_depth_c > 1) generate
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fifo.match <= '1' when (fifo.r_pnt(fifo.r_pnt'left-1 downto 0) = fifo.w_pnt(fifo.w_pnt'left-1 downto 0)) else '0';
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fifo.full <= '1' when (fifo.r_pnt(fifo.r_pnt'left) /= fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
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fifo.empty <= '1' when (fifo.r_pnt(fifo.r_pnt'left) = fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
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@ -136,7 +133,7 @@ begin
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end generate;
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check_small:
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if (FIFO_DEPTH = 1) generate
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if (fifo_depth_c = 1) generate
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fifo.match <= '1' when (fifo.r_pnt(0) = fifo.w_pnt(0)) else '0';
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fifo.full <= not fifo.match;
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fifo.empty <= fifo.match;
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@ -176,7 +173,7 @@ begin
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-- FIFO Memory - Write --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fifo_memory: -- real FIFO memory (several entries)
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if (FIFO_DEPTH > 1) generate
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if (fifo_depth_c > 1) generate
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sync_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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@ -189,7 +186,7 @@ begin
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end generate;
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fifo_buffer: -- simple register (single entry)
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if (FIFO_DEPTH = 1) generate
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if (fifo_depth_c = 1) generate
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sync_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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@ -208,7 +205,7 @@ begin
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if (FIFO_RSYNC = false) generate
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async_read: process(fifo)
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begin
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if (FIFO_DEPTH = 1) then
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if (fifo_depth_c = 1) then
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rdata_o <= fifo.buf;
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else
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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@ -221,7 +218,7 @@ begin
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async_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (FIFO_DEPTH = 1) then
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if (fifo_depth_c = 1) then
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rdata_o <= fifo.buf;
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else
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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