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[sw] minor edits/fixes

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- console output edits
- procesor_check: test if PMP test fails because of locked PMP entry
- fixed minor issue in number of PMP entries evaluation
This commit is contained in:
stnolting 2021-10-08 23:03:04 +02:00
parent 948c4dc045
commit 786dc0e0f7
2 changed files with 19 additions and 16 deletions
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29
sw/example/processor_check/main.c
View file

@ -758,7 +758,7 @@ int main() {
// Machine timer interrupt (MTIME)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] MTI (via MTIME): ", cnt_test);
PRINT_STANDARD("[%i] MTI (MTIME): ", cnt_test);
cnt_test++;
@ -793,7 +793,7 @@ int main() {
// Machine software interrupt (MSI) via testbench
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] MSI (via testbench): ", cnt_test);
PRINT_STANDARD("[%i] MSI (testbench): ", cnt_test);
cnt_test++;
@ -822,7 +822,7 @@ int main() {
// Machine external interrupt (MEI) via testbench
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] MEI (via testbench): ", cnt_test);
PRINT_STANDARD("[%i] MEI (testbench): ", cnt_test);
cnt_test++;
@ -881,7 +881,7 @@ int main() {
// Test pending interrupt
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] Pending IRQ(MTIME): ", cnt_test);
PRINT_STANDARD("[%i] Pending IRQ (MTIME): ", cnt_test);
cnt_test++;
@ -930,7 +930,7 @@ int main() {
// ----------------------------------------------------------
if (neorv32_wdt_available()) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ0(via WDT): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ0 (WDT): ", cnt_test);
cnt_test++;
@ -961,7 +961,7 @@ int main() {
// ----------------------------------------------------------
// Fast interrupt channel 1 (CFS)
// ----------------------------------------------------------
PRINT_STANDARD("[%i] FIRQ1(via CFS): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ1 (CFS): ", cnt_test);
PRINT_STANDARD("skipped \n");
@ -970,7 +970,7 @@ int main() {
// ----------------------------------------------------------
if (neorv32_uart1_available()) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ2(via UART0.RX): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ2 (UART0.RX): ", cnt_test);
cnt_test++;
@ -1014,7 +1014,7 @@ int main() {
// ----------------------------------------------------------
if (neorv32_uart0_available()) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ3(via UART0.TX): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ3 (UART0.TX): ", cnt_test);
cnt_test++;
@ -1058,7 +1058,7 @@ int main() {
// ----------------------------------------------------------
if (neorv32_uart1_available()) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ4(via UART1.RX): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ4 (UART1.RX): ", cnt_test);
cnt_test++;
@ -1099,7 +1099,7 @@ int main() {
// ----------------------------------------------------------
if (neorv32_uart1_available()) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ5(via UART1.TX): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ5 (UART1.TX): ", cnt_test);
cnt_test++;
@ -1140,7 +1140,7 @@ int main() {
// ----------------------------------------------------------
if (neorv32_spi_available()) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ6(via SPI): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ6 (SPI): ", cnt_test);
cnt_test++;
@ -1175,7 +1175,7 @@ int main() {
// ----------------------------------------------------------
if (neorv32_twi_available()) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ7(via TWI): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ7 (TWI): ", cnt_test);
cnt_test++;
@ -1209,7 +1209,7 @@ int main() {
// Fast interrupt channel 8 (XIRQ)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ8(via XIRQ): ", cnt_test);
PRINT_STANDARD("[%i] FIRQ8 (XIRQ): ", cnt_test);
if (neorv32_xirq_available()) {
cnt_test++;
@ -1415,6 +1415,9 @@ int main() {
test_ok();
}
else {
if (neorv32_cpu_csr_read(CSR_PMPCFG0) & 0x80) {
PRINT_CRITICAL("%c[1m<Entry LOCKED!> %c[0m\n", 27, 27);
}
test_fail();
}

6
sw/lib/source/neorv32_cpu.c
View file

@ -354,9 +354,9 @@ uint32_t neorv32_cpu_pmp_get_num_regions(void) {
uint32_t i = 0;
// try setting R bit in all PMPCFG CSRs
const uint32_t tmp = 0x01010101;
const uint32_t mask = 0x01010101;
for (i=0; i<16; i++) {
__neorv32_cpu_pmp_cfg_write(i, tmp);
__neorv32_cpu_pmp_cfg_write(i, mask);
}
// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
@ -367,7 +367,7 @@ uint32_t neorv32_cpu_pmp_get_num_regions(void) {
cnt.uint32 = 0;
for (i=0; i<16; i++) {
cnt.uint32 += __neorv32_cpu_pmp_cfg_read(i);
cnt.uint32 += __neorv32_cpu_pmp_cfg_read(i) & mask;
}
// sum up bytes