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[rtl] minor cleanups

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stnolting 2024-12-29 17:27:24 +01:00
parent f8b06121bd
commit 78854f2661
3 changed files with 9 additions and 12 deletions
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5
rtl/core/neorv32_bus.vhd
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@ -1,8 +1,5 @@
-- ================================================================================ --
-- NEORV32 SoC - Processor Bus Infrastructure: Prioritizing 2-to-1 Bus Switch --
-- -------------------------------------------------------------------------------- --
-- Allows to access a single device bus X by two controller ports A and B. --
-- Controller port A has priority over controller port B. --
-- NEORV32 SoC - Processor Bus Infrastructure: 2-to-1 Bus Switch --
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --

12
rtl/core/neorv32_debug_auth.vhd
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@ -1,5 +1,5 @@
-- ================================================================================ --
-- NEORV32 SoC - RISC-V-Compatible Authentication Module for the On-Chip Debugger --
-- NEORV32 OCD - RISC-V-Compatible Authentication Module for the On-Chip Debugger --
-- -------------------------------------------------------------------------------- --
-- Note that this module (in its default state) just provides a very simple and --
-- UNSECURE authentication mechanism that is meant as an example to showcase the --
@ -39,7 +39,7 @@ end neorv32_debug_auth;
architecture neorv32_debug_auth_rtl of neorv32_debug_auth is
signal authenticated : std_ulogic;
signal authenticated_q : std_ulogic;
begin
@ -53,12 +53,12 @@ begin
dm_controller: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
authenticated <= '0';
authenticated_q <= '0';
elsif rising_edge(clk_i) then
if (enable_i = '0') then
authenticated <= '0'; -- clear authentication when disabled
authenticated_q <= '0'; -- clear authentication when disabled
elsif (we_i = '1') then
authenticated <= wdata_i(0); -- just write a 1 to authenticate
authenticated_q <= wdata_i(0); -- just write a "1" to authenticate
end if;
end if;
end process dm_controller;
@ -67,7 +67,7 @@ begin
busy_o <= '0'; -- this simple authenticator is always ready
-- authentication passed --
valid_o <= authenticated;
valid_o <= authenticated_q;
-- read data --
rdata_o <= (others => '0'); -- there is nothing to read here

4
rtl/core/neorv32_debug_dtm.vhd
View file

@ -1,5 +1,5 @@
-- ================================================================================ --
-- NEORV32 SoC - RISC-V-Compatible Debug Transport Module (DTM) --
-- NEORV32 OCD - RISC-V-Compatible Debug Transport Module (DTM) --
-- -------------------------------------------------------------------------------- --
-- Compatible to RISC-V debug spec. versions 0.13 and 1.0. --
-- -------------------------------------------------------------------------------- --
@ -111,7 +111,7 @@ begin
tap_sync.tdi <= tap_sync.tdi_ff(2);
-- Tap Control FSM ------------------------------------------------------------------------
-- JTAG Tap Control FSM -------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
tap_control: process(rstn_i, clk_i)
begin