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[ocd-firmware] minor edits
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1 changed files with 6 additions and 6 deletions
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@ -16,7 +16,7 @@
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.option norvc
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.global _ocd_start
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.global entry_exception
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.global entry_normal
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.global entry_park
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// debug module (DM) address map
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.equ DM_CODE_BASE, 0xFFFFFE00 // base address of code ROM (park loop)
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@ -40,11 +40,11 @@ _ocd_start:
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entry_exception:
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sw zero, (DM_SREG_BASE+ACK_EXC)(zero) // send exception-acknowledge (no need for a hart ID)
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csrr x8, dscratch0 // restore x8 from dscratch0 (might be changed during PBUF execution)
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ebreak // re-enter debug mode (at "entry_normal" entry point)
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nop
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ebreak // re-enter debug mode (at "entry_park" entry point)
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nop // dummy to align the address of "entry_park"
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// BASE + 16: normal entry - ebreak in debug-mode, halt request or return from single-stepped instruction
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entry_normal:
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// BASE + 16: normal entry - halt CPU: ebreak in debug-mode, halt request or return from single-stepped instruction
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entry_park:
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csrw dscratch0, x8 // backup x8 to dscratch0 so we have a GPR available
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csrr x8, mhartid // get hart ID (0..3)
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sw x8, (DM_SREG_BASE+ACK_HLT)(zero) // send halt-acknowledge
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@ -68,7 +68,7 @@ resume:
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csrr x8, dscratch0 // restore x8 from dscratch0
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dret // exit debug mode
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// execute program buffer (implicit ebreak at the end of the buffer will bring us back to 'entry_normal')
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// execute program buffer (implicit ebreak at the end of the buffer will bring us back to "entry_park")
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execute:
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csrr x8, mhartid // get hart ID (0..3)
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sw x8, (DM_SREG_BASE+ACK_EXE)(zero) // send execute-acknowledge
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