[docs] TWD: minor edits and fixes

docs/datasheet/soc_twd.adoc

@@ -30,7 +30,7 @@ Key features:
 * Programmable 7-bit device address
 * Programmable interrupt conditions
 * Configurable RX/TX data FIFO to "program" large TWD sequences without further involvement of the CPU
-* Optional dummy TX byte which gets read when the TX FIFO is empty
+* Optional dummy TX byte which gets send to the bus if the TX FIFO is drained
 
 .Device-Mode Only
 [NOTE]
@@ -43,13 +43,12 @@ check out the <<_two_wire_serial_interface_controller_twi>>.
 
 The TWD module provides two memory-mapped registers that are used for configuration & status check (`CTRL`) and
 for accessing transmission data (`DATA`). The `DATA` register is transparently buffered by separate RX and TX FIFOs.
-The size of those FIFOs can be configured by the `IO_TWD_RX_FIFO` and `IO_TWD_TX_FIFO` generics. Software can determine the FIFO size via the control register's 
-`TWD_CTRL_FIFO_*` bits.
-
-In addition to the TX FIFO itself, there is a dummy byte register that stores the last TX FIFO byte.
+The size of those FIFOs can be configured by the `IO_TWD_RX_FIFO` and `IO_TWD_TX_FIFO` generics. Software can determine
+the FIFO size via the control register's `TWD_CTRL_FIFO_*` bits. The current status of the RX and TX FIFO can be polled
+by software via the `TWD_CTRL_RX_*` and `TWD_CTRL_TX_*` flags.
 
 The module is globally enabled by setting the control register's `TWD_CTRL_EN` bit. Clearing this bit will disable
-and reset the entire module also clearing the internal RX and TX FIFOs, but not the dummy byte. Each FIFO can also be cleared individually at
+and reset the entire module also clearing the internal RX and TX FIFOs. Each FIFO can also be cleared individually at
 any time by setting `TWD_CTRL_CLR_RX` or `TWD_CTRL_CLR_TX`, respectively.
 
 The external two wire bus is sampled sampled and synchronized into the processor's clock domain with a sampling
@@ -67,13 +66,14 @@ addresses are not supported.
 
 Depending on the transaction type, data is either read from the RX FIFO and transferred to the host ("read operation")
 or data is received from the host and written to the TX FIFO ("write operation"). Hence, data sequences can be
-programmed to the TX FIFO to be fetched from the host. If the TX FIFO is empty and the host keeps performing read
-transaction, either the dummy byte gets read when enabled or the read will be not acknowledged.
+programmed to the TX FIFO to be fetched from the host.
 
-The dummy behavior can be used by the host to perform polling, for example, to check the status of the device.
+If the TX FIFO is empty or drained and the host keeps performing read transactions, one out of three behaviors can
+be selected:
 
-The current status of the RX and TX FIFO can be polled by software via the `TWD_CTRL_RX_*` and `TWD_CTRL_TX_*`
-flags.
+* send all-one to the bus (default)
+* send the last byte that was taken from the TX FIFO to the bus if `TWD_CTRL_TX_DUMMY_EN` is set
+* send nothing and respond with no ACK (i.e. the TWD "disappears" from the bus) if `TWD_CTRL_HIDE_READ` is set
 
 
 **TWD Interrupt**
@@ -141,11 +141,10 @@ or **read** (leaving the SDA line high). If the transferred address matches the
 control register bits the TWD module will response with an **ACK** (acknowledge) by pulling the SDA bus line actively
 low during the 9th SCL clock pulse. If there is no address match the TWD will not interfere with the bus and move back
 to idle state.
-If the `hide_read` option is enabled, the address gets not acknowledged if the tx fifo is empty.
 
 For a **write transaction** (upper timing diagram) the host can now transfer an arbitrary number of bytes (blue signals
 `D7` to `D0`, MSB-first) to the TWD module. Each byte is acknowledged by the TWD by pulling SDA low during the 9th SCL
-clock pules (**ACK**), if moved into the fifo. When the fifo is full, the transfer gets not acknowledged (**NACK**).
+clock pules (**ACK**), if moved into the FIFO. When the FIFO is full, the transfer gets not acknowledged (**NACK**).
 Each received data byte is pushed to the internal RX FIFO. Data will be lost if the FIFO overflows.
 The transaction is terminated when the host issues a **STOP** condition after the TWD has acknowledged the last data
 transfer.
@@ -154,9 +153,11 @@ For a **read transaction** (lower timing diagram) the host keeps the SDA line at
 pulse. The TWD will read a byte from the internal TX FIFO and will transmit it MSB-first to the host (blue signals `D7`
 to `D0)`. During the 9th clock pulse the host has to acknowledged the transfer (**ACK**) by pulling SDA low. If no ACK
 is received by the TWD no data is taken from the TX FIFO and the same byte can be transmitted in the next data phase.
-If the TX FIFO becomes empty while the host keeps reading data, all-one bytes are transmitted. To terminate the
+If the TX FIFO becomes empty while the host keeps reading data, all-one bytes are transmitted (if `TWD_CTRL_TX_DUMMY_EN = 0`)
+or the last value taken from the TX FIFO (before it got empty is sent again (`TWD_CTRL_TX_DUMMY_EN = 1`). To terminate the
 transmission the host hast so send a **NACK** after receiving the last data byte by keeping SDA high. After that, the
-host has to issue a **STOP** condition.
+host has to issue a **STOP** condition. If the `TWD_CTRL_HIDE_READ` bit is set, the access will not get acknowledged
+at all if the TX FIFO is empty.
 
 A **repeated-START** condition can be issued at any time (but after the complete transaction of a data byte and there
 according ACK/NACK) bringing the TWD back to the start of the address/command transmission phase. The control register's