faste synthesis due to less copy iterations during memory initialization

rtl/core/neorv32_boot_rom.vhd

@@ -56,10 +56,12 @@ architecture neorv32_boot_rom_rtl of neorv32_boot_rom is
   type boot_img_t is array (0 to boot_size_c/4-1) of std_ulogic_vector(31 downto 0);
 
   -- init function --
+  -- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
   impure function init_boot_rom(init : bootloader_init_image_t) return boot_img_t is
     variable mem_v : boot_img_t;
   begin
-    for i in 0 to boot_size_c/4-1 loop
+    mem_v := (others => (others => '0'));
+    for i in 0 to init'length-1 loop -- init only in range of source data array
       mem_v(i) := init(i);
     end loop; -- i
     return mem_v;

rtl/core/neorv32_imem.vhd

@@ -71,19 +71,13 @@ architecture neorv32_imem_rtl of neorv32_imem is
   type imem_file8_t is array (0 to IMEM_SIZE/4-1) of std_ulogic_vector(07 downto 0);
 
   -- init function and split 1x32-bit memory into 4x8-bit memories --
+  -- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
   impure function init_imem(byte : natural; init : application_init_image_t) return imem_file8_t is
     variable mem_v : imem_file8_t;
   begin
-    for i in 0 to IMEM_SIZE/4-1 loop
-      if (byte = 0) then -- lowest byte
-        mem_v(i) := init(i)(07 downto 00);
-      elsif (byte = 1) then
-        mem_v(i) := init(i)(15 downto 08);
-      elsif (byte = 2) then
-        mem_v(i) := init(i)(23 downto 16);
-      else -- highest byte
-        mem_v(i) := init(i)(31 downto 24);
-      end if;
+    mem_v := (others => (others => '0'));
+    for i in 0 to init'length-1 loop -- init only in range of source data array
+        mem_v(i) := init(i)(byte*8+7 downto byte*8+0);
     end loop; -- i
     return mem_v;
   end function init_imem;
@@ -94,6 +88,9 @@ architecture neorv32_imem_rtl of neorv32_imem is
   signal rden   : std_ulogic;
   signal addr   : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
 
+  -- The memory is built from 4x byte-wide memories defined as unique signals, since many synthesis tools
+  -- have problems with 32-bit memories with byte-enable signals or with multi-dimensional arrays.
+
   -- internal "RAM" type - implemented if bootloader is used and IMEM is RAM and initialized with app code --
   signal imem_file_init_ram_ll : imem_file8_t := init_imem(0, application_init_image);
   signal imem_file_init_ram_lh : imem_file8_t := init_imem(1, application_init_image);
@@ -113,6 +110,7 @@ architecture neorv32_imem_rtl of neorv32_imem is
   signal imem_file_ram_hh : imem_file8_t;
 
 
+  -- -------------------------------------------------------------------------------- --
   -- attributes - these are *NOT mandatory*; just for footprint / timing optimization --
   -- -------------------------------------------------------------------------------- --
 

rtl/core/neorv32_package.vhd

@@ -41,7 +41,7 @@ package neorv32_package is
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   constant data_width_c  : natural := 32; -- data width - FIXED!
-  constant hw_version_c  : std_ulogic_vector(31 downto 0) := x"01030703"; -- no touchy!
+  constant hw_version_c  : std_ulogic_vector(31 downto 0) := x"01030800"; -- no touchy!
   constant pmp_max_r_c   : natural := 8; -- max PMP regions
   constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2