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https://github.com/stnolting/neorv32.git
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[cpu] add new counters module
This commit is contained in:
stnolting
parent
34b6ad4e7f
commit
7f6b609316
2 changed files with 385 additions and 6 deletions
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@ -105,7 +105,7 @@ architecture neorv32_cpu_rtl of neorv32_cpu is
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RISCV_ISA_Zksh and RISCV_ISA_Zksed; -- Zks: ShangMi suite
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-- external CSR interface read-back --
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signal xcsr_pmp, xcsr_alu, xcsr_res, xcsr_icc : std_ulogic_vector(XLEN-1 downto 0);
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signal xcsr_cnt, xcsr_pmp, xcsr_alu, xcsr_res, xcsr_icc : std_ulogic_vector(XLEN-1 downto 0);
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-- local signals --
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signal ctrl : ctrl_bus_t; -- main control bus
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@ -269,10 +269,7 @@ begin
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CPU_CLOCK_GATING_EN => CPU_CLOCK_GATING_EN, -- enable clock gating when in sleep mode
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CPU_FAST_MUL_EN => CPU_FAST_MUL_EN, -- use DSPs for M extension's multiplier
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CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN, -- use barrel shifter for shift operations
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CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN, -- implement full hardware reset for register file
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..13)
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HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters
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CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN -- implement full hardware reset for register file
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)
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port map (
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-- global control --
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@ -307,7 +304,34 @@ begin
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irq_machine <= mti_i & mei_i & msi_i;
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-- control-external CSR read-back --
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xcsr_res <= xcsr_alu or xcsr_pmp or xcsr_icc;
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xcsr_res <= xcsr_cnt or xcsr_alu or xcsr_pmp or xcsr_icc;
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-- Hardware Counters ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cnts_enabled:
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if RISCV_ISA_Zicntr or RISCV_ISA_Zihpm generate
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neorv32_cpu_counters_inst: entity neorv32.neorv32_cpu_counters
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generic map (
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ZICNTR_EN => RISCV_ISA_Zicntr, -- implement base counters
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ZIHPM_EN => RISCV_ISA_Zihpm, -- implement hardware performance monitors
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HPM_NUM => HPM_NUM_CNTS, -- number of implemented HPM counters (0..13)
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HPM_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (0..64)
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)
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port map (
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-- global control --
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clk_i => clk_gated, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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-- read back --
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rdata_o => xcsr_cnt -- read data
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);
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end generate;
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cnts_disabled:
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if (not RISCV_ISA_Zicntr) and (not RISCV_ISA_Zihpm) generate
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xcsr_cnt <= (others => '0');
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end generate;
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-- Register File --------------------------------------------------------------------------
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355
rtl/core/neorv32_cpu_counters.vhd
Normal file
355
rtl/core/neorv32_cpu_counters.vhd
Normal file
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@ -0,0 +1,355 @@
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-- ================================================================================ --
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-- NEORV32 CPU - Hardware Counters --
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-- -------------------------------------------------------------------------------- --
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-- Implementing hardware counters for the following RISC-V ISA extensions: --
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-- + Zicntr: Base Counters -> [m]cycle[h] + [m]time[h] + [m]instret[h] CSRs --
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-- + Zihpm: Hardware Performance Monitors -> [m]hpmcntx[h] + mhpmeventx CRSs --
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-- -------------------------------------------------------------------------------- --
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-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
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-- Copyright (c) NEORV32 contributors. --
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-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
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-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
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-- SPDX-License-Identifier: BSD-3-Clause --
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-- ================================================================================ --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_counters is
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generic (
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ZICNTR_EN : boolean; -- implement base counters
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ZIHPM_EN : boolean; -- implement hardware performance monitors
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HPM_NUM : natural range 0 to 13; -- number of implemented HPM counters (0..13)
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HPM_WIDTH : natural range 0 to 64 -- total size of HPM counters (0..64)
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in ctrl_bus_t; -- main control bus
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-- read back --
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rdata_o : out std_ulogic_vector(XLEN-1 downto 0) -- read data
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);
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end neorv32_cpu_counters;
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architecture neorv32_cpu_counters_rtl of neorv32_cpu_counters is
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-- generic counter module --
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component neorv32_cpu_counters_cnt
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generic (
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CNT_WIDTH : natural range 0 to 64 -- counter width (0..64)
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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inc_i : in std_ulogic; -- enable counter increment
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-- read/write access --
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sel_i : in std_ulogic; -- high word / low word select
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we_i : in std_ulogic; -- write enable
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re_i : in std_ulogic; -- read enable
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wdata_i : in std_ulogic_vector(XLEN-1 downto 0); -- write data
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rdata_o : out std_ulogic_vector(XLEN-1 downto 0) -- read data
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);
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end component;
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-- global access decoder --
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signal cnt_acc, cfg_acc : std_ulogic;
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signal sel, cnt_we, cnt_re, cfg_we, cfg_re : std_ulogic_vector(15 downto 0);
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-- counter increment control --
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signal cnt_en : std_ulogic_vector(15 downto 0);
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-- individual HPM read-backs --
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type hpmevent_t is array (3 to 15) of std_ulogic_vector(11 downto 0);
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type hpmcnt_t is array (3 to 15) of std_ulogic_vector(XLEN-1 downto 0);
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signal hpmevent : hpmevent_t;
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signal hpmcnt : hpmcnt_t;
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-- global read-backs --
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signal cycle_rd, time_rd, instret_rd, hpm_rd : std_ulogic_vector(XLEN-1 downto 0);
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begin
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-- Access Decoder -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_gen:
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for i in 0 to 15 generate
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sel(i) <= '1' when (ctrl_i.csr_addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) else '0';
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cnt_we(i) <= cnt_acc and sel(i) and ctrl_i.csr_we;
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cnt_re(i) <= cnt_acc and sel(i) and ctrl_i.csr_re;
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cfg_we(i) <= cfg_acc and sel(i) and ctrl_i.csr_we;
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cfg_re(i) <= cfg_acc and sel(i) and ctrl_i.csr_re;
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end generate;
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-- global access --
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cnt_acc <= '1' when ZICNTR_EN and ((ctrl_i.csr_addr(11 downto 5) = csr_cycle_c(11 downto 5)) or
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(ctrl_i.csr_addr(11 downto 5) = csr_mcycle_c(11 downto 5)) or
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(ctrl_i.csr_addr(11 downto 5) = csr_cycleh_c(11 downto 5)) or
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(ctrl_i.csr_addr(11 downto 5) = csr_mcycleh_c(11 downto 5))) else '0';
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cfg_acc <= '1' when ZIHPM_EN and (ctrl_i.csr_addr(11 downto 5) = csr_mhpmevent3_c(11 downto 5)) else '0';
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-- global data read-back --
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rdata_o <= cycle_rd or time_rd or instret_rd or hpm_rd;
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-- Counter Increment Control --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cnt_control: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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cnt_en <= (others => '0');
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elsif rising_edge(clk_i) then
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-- increment if an (enabled) event fires; do not increment if CPU is in debug mode or if counter is inhibited
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cnt_en(0) <= ctrl_i.cnt_event(cnt_event_cy_c) and (not ctrl_i.cpu_debug) and (not ctrl_i.cnt_halt(0));
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cnt_en(1) <= '0'; -- time: not available
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cnt_en(2) <= ctrl_i.cnt_event(cnt_event_ir_c) and (not ctrl_i.cpu_debug) and (not ctrl_i.cnt_halt(2));
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for i in 3 to 15 loop
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cnt_en(i) <= or_reduce_f(ctrl_i.cnt_event and hpmevent(i)) and (not ctrl_i.cpu_debug) and (not ctrl_i.cnt_halt(i));
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end loop;
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end if;
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end process cnt_control;
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-- Base Counters (Zicntr) -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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base_enabled:
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if ZICNTR_EN generate
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-- [m]cycle[h] CSR --
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cycle_inst: neorv32_cpu_counters_cnt
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generic map (
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CNT_WIDTH => 2*XLEN
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)
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port map (
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clk_i => clk_i,
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rstn_i => rstn_i,
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inc_i => cnt_en(0),
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sel_i => ctrl_i.csr_addr(7),
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we_i => cnt_we(0),
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re_i => cnt_re(0),
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wdata_i => ctrl_i.csr_wdata,
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rdata_o => cycle_rd
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);
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-- [m]time[h] CSR --
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time_rd <= (others => '0'); -- not implemented (yet?)
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-- [m]instret[h] CSR --
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instret_inst: neorv32_cpu_counters_cnt
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generic map (
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CNT_WIDTH => 2*XLEN
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)
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port map (
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clk_i => clk_i,
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rstn_i => rstn_i,
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inc_i => cnt_en(2),
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sel_i => ctrl_i.csr_addr(7),
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we_i => cnt_we(2),
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re_i => cnt_re(2),
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wdata_i => ctrl_i.csr_wdata,
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rdata_o => instret_rd
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);
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end generate; -- /base_enabled
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base_disabled:
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if not ZICNTR_EN generate
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cycle_rd <= (others => '0');
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time_rd <= (others => '0');
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instret_rd <= (others => '0');
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end generate; -- /base__disabled
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-- Hardware Performance Monitors (Zihpm) --------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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hpm_enabled:
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if ZIHPM_EN and (HPM_NUM > 0) generate
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hpm_gen:
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for i in 3 to (HPM_NUM+3)-1 generate
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-- [m]hpmcntx[h] CSRs --
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hpmcnt_inst: neorv32_cpu_counters_cnt
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generic map (
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CNT_WIDTH => HPM_WIDTH
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)
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port map (
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clk_i => clk_i,
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rstn_i => rstn_i,
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inc_i => cnt_en(i),
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sel_i => ctrl_i.csr_addr(7),
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we_i => cnt_we(i),
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re_i => cnt_re(i),
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wdata_i => ctrl_i.csr_wdata,
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rdata_o => hpmcnt(i)
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);
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-- mhpmeventx CSRs --
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hpmevent_reg: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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hpmevent(i) <= (others => '0');
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elsif rising_edge(clk_i) then
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if (cfg_we(i) = '1') then
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hpmevent(i) <= ctrl_i.csr_wdata(11 downto 0);
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end if;
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hpmevent(i)(cnt_event_tm_c) <= '0'; -- time: not available
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end if;
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end process hpmevent_reg;
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end generate; -- /hpm_gen
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-- terminate unused entries --
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hpm_terminate_gen:
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for i in HPM_NUM+3 to 15 generate
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hpmcnt(i) <= (others => '0');
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hpmevent(i) <= (others => '0');
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end generate; -- /hpm_terminate_gen
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-- read-back --
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hpm_read_back: process(hpmcnt, cfg_re, hpmevent)
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variable cnt_v, cfg_v : std_ulogic_vector(XLEN-1 downto 0);
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begin
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cnt_v := (others => '0');
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cfg_v := (others => '0');
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for i in 3 to 15 loop
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cnt_v := cnt_v or hpmcnt(i);
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if (cfg_re(i) = '1') then -- gating
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cfg_v := cfg_v or std_ulogic_vector(resize(unsigned(hpmevent(i)), XLEN));
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end if;
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end loop;
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hpm_rd <= cnt_v or cfg_v;
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end process hpm_read_back;
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end generate; -- /hpm_enabled
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hpm_disabled:
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if (not ZIHPM_EN) or (HPM_NUM = 0) generate
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hpmcnt <= (others => (others => '0'));
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hpmevent <= (others => (others => '0'));
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hpm_rd <= (others => '0');
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end generate; -- /hpm_disabled
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end neorv32_cpu_counters_rtl;
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-- ================================================================================ --
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-- NEORV32 CPU - Generic Counter Module --
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-- -------------------------------------------------------------------------------- --
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-- If the counter is wider than 32 bit it is split into two sub-word registers in --
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-- order to shorten the carry chain length by inserting a flip flop stage. --
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-- -------------------------------------------------------------------------------- --
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-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
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-- Copyright (c) NEORV32 contributors. --
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-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
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-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
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-- SPDX-License-Identifier: BSD-3-Clause --
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-- ================================================================================ --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_counters_cnt is
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generic (
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CNT_WIDTH : natural range 0 to 64 -- counter width (0..64)
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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inc_i : in std_ulogic; -- enable counter increment
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-- read/write access --
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sel_i : in std_ulogic; -- high word / low word select
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we_i : in std_ulogic; -- write enable
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re_i : in std_ulogic; -- read enable
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wdata_i : in std_ulogic_vector(XLEN-1 downto 0); -- write data
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rdata_o : out std_ulogic_vector(XLEN-1 downto 0) -- read data
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);
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end neorv32_cpu_counters_cnt;
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architecture neorv32_cpu_counters_cnt_rtl of neorv32_cpu_counters_cnt is
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-- sub-word size configuration --
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constant lo_width_c : natural := min_natural_f(CNT_WIDTH, 32); -- size low word
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constant hi_width_c : natural := CNT_WIDTH - lo_width_c; -- size high word
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-- core --
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signal lo_q : std_ulogic_vector(lo_width_c-1 downto 0);
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signal hi_q : std_ulogic_vector(hi_width_c-1 downto 0);
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signal cy_q : std_ulogic_vector(0 downto 0);
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signal nxt : std_ulogic_vector(lo_width_c downto 0);
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signal inc : std_ulogic_vector(0 downto 0);
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begin
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-- counter low-word --
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low_reg: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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lo_q <= (others => '0');
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elsif rising_edge(clk_i) then
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if (we_i = '1') and (sel_i = '0') then
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lo_q <= wdata_i(lo_width_c-1 downto 0);
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else
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lo_q <= nxt(lo_width_c-1 downto 0);
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end if;
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end if;
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end process low_reg;
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-- low-word increment --
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inc <= (others => inc_i);
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nxt <= std_ulogic_vector(unsigned('0' & lo_q) + unsigned(inc));
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-- counter high-word --
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high_word_enabled:
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if (CNT_WIDTH > 32) generate
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high_reg: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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cy_q <= (others => '0');
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hi_q <= (others => '0');
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elsif rising_edge(clk_i) then
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cy_q <= (others => nxt(lo_width_c)); -- low-word to high-word carry
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if (we_i = '1') and (sel_i = '1') then
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hi_q <= wdata_i(hi_width_c-1 downto 0);
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else
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hi_q <= std_ulogic_vector(unsigned(hi_q) + unsigned(cy_q));
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end if;
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end if;
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end process high_reg;
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end generate;
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high_word_disabled:
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if (CNT_WIDTH <= 32) generate
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cy_q <= (others => '0');
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hi_q <= (others => '0');
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end generate;
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-- output selected sub-word --
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output_select: process(re_i, sel_i, lo_q, hi_q)
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begin
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rdata_o <= (others => '0');
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if (re_i = '1') and (CNT_WIDTH > 0) then
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if (sel_i = '0') or (CNT_WIDTH <= 32) then
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rdata_o <= std_ulogic_vector(resize(unsigned(lo_q), XLEN));
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else
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rdata_o <= std_ulogic_vector(resize(unsigned(hi_q), XLEN));
|
||||
end if;
|
||||
end if;
|
||||
end process output_select;
|
||||
|
||||
end neorv32_cpu_counters_cnt_rtl;
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue