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https://github.com/stnolting/neorv32.git
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[sw/example/demo_spi_irq]: change driver to accept only byte orientated transfers, api of neorv32_spi_rw changed
This commit is contained in:
Andreas Kaeberlein
parent
676709dbed
commit
83d4450dd2
3 changed files with 28 additions and 93 deletions
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@ -68,77 +68,30 @@ void neorv32_spi_init(t_neorv32_spi *self) {
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**************************************************************************/
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void neorv32_spi_isr(t_neorv32_spi *self) {
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volatile uint32_t uint32Buf; // help variable
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uint32_t uint32Lim; // loop limit
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uint32_t uint32Lim; // loop limit
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if ( 0 == self->uint32Total ) { // leave if accidentally called ISR
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return;
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}
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switch (self->uint8SzElem) {
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case 1: // uint8_t
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// read data from SPI from last transfer
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for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
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((uint8_t *) self->ptrSpiBuf)[self->uint32Read] = (uint8_t) (NEORV32_SPI->DATA & 0xff); // capture from last transfer
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}
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if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
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neorv32_spi_cs_dis(); // deselect slave
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self->uint32Total = 0;
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self->uint8IsBusy = 0;
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break;
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}
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// write next packet
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uint32Lim = min(self->uint32Write+self->uint16Fifo, self->uint32Total);
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for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
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uint32Buf = 0;
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uint32Buf |= ((uint8_t *) self->ptrSpiBuf)[self->uint32Write];
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NEORV32_SPI->DATA = uint32Buf; // next transfer
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}
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break;
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case 2: // uint16_t
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// read data from SPI from last transfer
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for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
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((uint16_t *) self->ptrSpiBuf)[self->uint32Read] = (uint16_t) (NEORV32_SPI->DATA & 0xffff); // capture from last transfer
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}
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if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
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neorv32_spi_cs_dis(); // deselect slave
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self->uint32Total = 0;
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self->uint8IsBusy = 0;
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break;
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}
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// write next packet
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uint32Lim = min(self->uint32Write+self->uint16Fifo, self->uint32Total);
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for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
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uint32Buf = 0;
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uint32Buf |= ((uint16_t *) self->ptrSpiBuf)[self->uint32Write];
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NEORV32_SPI->DATA = uint32Buf; // next transfer
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}
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break;
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case 4: // uint32_t
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// read data from SPI from last transfer
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for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
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((uint32_t *) self->ptrSpiBuf)[self->uint32Read] = NEORV32_SPI->DATA; // capture from last transfer
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}
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if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
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neorv32_spi_cs_dis(); // deselect slave
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self->uint32Total = 0;
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self->uint8IsBusy = 0;
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break;
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}
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// write next packet
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uint32Lim = min(self->uint32Write+self->uint16Fifo, self->uint32Total);
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for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
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uint32Buf = 0;
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uint32Buf |= ((uint32_t *) self->ptrSpiBuf)[self->uint32Write];
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NEORV32_SPI->DATA = uint32Buf; // next transfer
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}
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break;
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default: // unknown
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break;
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// read data from SPI from last transfer
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for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
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(self->ptrSpiBuf)[self->uint32Read] = (uint8_t) (NEORV32_SPI->DATA & 0xff); // capture from last transfer
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}
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if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
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neorv32_spi_cs_dis(); // deselect slave
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self->uint32Total = 0;
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self->uint8IsBusy = 0;
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neorv32_cpu_csr_clr(CSR_MIP, 1 << SPI_FIRQ_PENDING); // ack/clear pending FIRQ
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return;
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}
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// write next packet
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uint32Lim = min(self->uint32Write+self->uint16Fifo, self->uint32Total);
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for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
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NEORV32_SPI->DATA = (uint32_t) (self->ptrSpiBuf)[self->uint32Write]; // next transfer
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}
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neorv32_cpu_csr_clr(CSR_MIP, 1 << SPI_FIRQ_PENDING); // ack/clear pending FIRQ
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return;
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}
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@ -147,49 +100,31 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
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* Starts ISR driven read/write SPI transfer.
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*
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* @param[in,out] *self SPI driver common data handle. See #t_neorv32_spi.
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* @param[in,out] *spi write/read data buffer for SPI. Before transmission contents the write data and after the read data.
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* @param[in] csn Used chip select index for transfer.
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* @param[in] num_elem Number of elements to transfer.
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* @param[in] data_byte Number of data bytes per element in *spi.
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* @param[in,out] *spi write/read data buffer for SPI. Before transmission contents the write data and after the read data.
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* @param[in] len number of bytes to transfer.
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* @return int status of function.
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* @retval 0 new transfer started.
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* @retval 1 transfer active, refused request.
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* @retval 2 unsupported data size, only 1/2/4 allowed.
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**************************************************************************/
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int neorv32_spi_rw(t_neorv32_spi *self, void *spi, uint8_t csn, uint32_t num_elem, uint8_t data_byte) {
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volatile uint32_t uint32Buf; // help variable
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int neorv32_spi_rw(t_neorv32_spi *self, uint8_t csn, void *spi, uint32_t len) {
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if ( 0 != self->uint8IsBusy ) {
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return 1; // transfer active, no new request
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}
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self->uint32Total = num_elem;
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self->uint32Total = len;
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self->uint32Write = 0; // write element count
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self->uint32Read = 0; // read element count
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self->ptrSpiBuf = spi;
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self->uint8SzElem = data_byte;
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self->ptrSpiBuf = (uint8_t*) spi; // spi is byte orientated
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self->uint8Csn = csn;
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self->uint8IsBusy = 1; // mark as busy
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neorv32_spi_cs_en(self->uint8Csn); // select SPI channel
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uint32Buf = 0;
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switch (self->uint8SzElem) { // start first transfer, rest is handled by ISR; can only sent one element, otherwise clash with ISR
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case 1: // uint8_t
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uint32Buf |= ((uint8_t *) self->ptrSpiBuf)[0];
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break;
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case 2: // uint16_t
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uint32Buf |= ((uint16_t *) self->ptrSpiBuf)[0];
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break;
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case 4: // uint32_t
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uint32Buf = ((uint32_t *) self->ptrSpiBuf)[0];
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break;
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default:
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return 2; // unsupported byte size
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}
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(self->uint32Write)++;
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NEORV32_SPI->DATA = uint32Buf; // next transfer
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(self->uint32Write)++;
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NEORV32_SPI->DATA = (uint32_t) (self->ptrSpiBuf)[0]; // sent first element
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return 0; // successful end
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}
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@ -54,8 +54,7 @@
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// data handle for ISR
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typedef struct t_neorv32_spi
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{
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void* ptrSpiBuf; /**< SPI buffer data pointer */
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uint8_t uint8SzElem; /**< Element Size in byte */
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uint8_t* ptrSpiBuf; /**< SPI buffer data pointer */
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uint8_t uint8Csn; /**< SPI chip select channel */
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uint16_t uint16Fifo; /**< Number of elements in Fifo */
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uint32_t uint32Total; /**< Number of elements in buffer */
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@ -68,7 +67,7 @@ typedef struct t_neorv32_spi
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// prototypes
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void neorv32_spi_init(t_neorv32_spi *self);
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void neorv32_spi_isr(t_neorv32_spi *self);
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int neorv32_spi_rw(t_neorv32_spi *self, void *spi, uint8_t csn, uint32_t num_elem, uint8_t data_byte);
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int neorv32_spi_rw(t_neorv32_spi *self, uint8_t csn, void *spi, uint32_t len);
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int neorv32_spi_rw_busy(t_neorv32_spi *self);
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#endif // neorv32_spi_irq_h
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@ -113,7 +113,7 @@ int main()
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neorv32_spi_init(&g_neorv32_spi);
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// Configure
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neorv32_spi_disable();
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// neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int data_size, int irq_config)
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// neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t irq_mask)
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neorv32_spi_setup(0, 0, 0, 0, 1<<SPI_CTRL_IRQ_TX_EMPTY); // spi mode 0, IRQ: 0-: PHY going idle, 10: TX fifo less than half full, 11: TX fifo empty
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neorv32_spi_enable();
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@ -123,7 +123,8 @@ int main()
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uint8MemBuf[1] = 0x0;
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uint8MemBuf[2] = 0x0;
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uint8MemBuf[3] = 0x0;
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neorv32_spi_rw(&g_neorv32_spi, uint8MemBuf, 0, sizeof(uint8MemBuf)/sizeof(uint8MemBuf[0]), sizeof(uint8MemBuf[0])); // send/receive data
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// int neorv32_spi_rw(t_neorv32_spi *self, uint8_t csn, void *spi, uint32_t len)
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neorv32_spi_rw(&g_neorv32_spi, 0, uint8MemBuf, sizeof(uint8MemBuf)); // send/receive data
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// Wait for complete, free for other jobs
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while ( neorv32_spi_rw_busy(&g_neorv32_spi) ) {
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