github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 14:17:51 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[!] disable C ext. for processor check

Browse source 
to check for correct handling of misaligned instruction exception; C extension is still tested/verified in neorv32-riscof
This commit is contained in:
stnolting 2023-11-21 21:15:19 +01:00
parent e6e20fd0b9
commit 8b231cf228
4 changed files with 5 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

2
do.py
View file

@ -26,7 +26,7 @@ def task_BuildAndInstallSoftwareFrameworkTests():
"make -C sw/bootloader clean_all info bootloader",
# Compile and install test application, redirect UART0 TX to text.io simulation output via <UARTx_SIM_MODE> user flags
"echo 'Compiling and installing CPU/Processor test application'",
"make -C sw/example/processor_check clean_all USER_FLAGS+=-DUART0_SIM_MODE USER_FLAGS+=-DUART1_SIM_MODE USER_FLAGS+=-flto EFFORT=-Os MARCH=rv32imac_zicsr_zifencei info all",
"make -C sw/example/processor_check clean_all USER_FLAGS+=-DUART0_SIM_MODE USER_FLAGS+=-DUART1_SIM_MODE USER_FLAGS+=-flto EFFORT=-Os MARCH=rv32ima_zicsr_zifencei info all",
],
"doc": "Build all sw/example/*; install bootloader and processor check",
}

4
sim/neorv32_tb.vhd
View file

@ -184,7 +184,7 @@ begin
if ci_mode then
-- No need to send the full expectation in one big chunk
check_uart(net, uart1_rx_handle, nul & nul);
check_uart(net, uart1_rx_handle, "0/57" & cr & lf);
check_uart(net, uart1_rx_handle, "0/58" & cr & lf);
end if;
-- Wait until all expected data has been received
@ -227,7 +227,7 @@ begin
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => true, -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B => true, -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_C => false, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?

2
sim/simple/neorv32_tb.simple.vhd
View file

@ -170,7 +170,7 @@ begin
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => true, -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B => true, -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_C => false, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?

2
sw/example/processor_check/run_check.sh
View file

@ -3,4 +3,4 @@
set -e
echo "Starting processor check simulation..."
make USER_FLAGS+="-DUART0_SIM_MODE -DUART1_SIM_MODE -g -flto" EFFORT=-Os MARCH=rv32imac_zicsr_zifencei clean_all all sim
make USER_FLAGS+="-DUART0_SIM_MODE -DUART1_SIM_MODE -g -flto" EFFORT=-Os MARCH=rv32ima_zicsr_zifencei clean_all all sim