update refs to the templates in the docs, boards, etc.

README.md

@@ -107,9 +107,9 @@ cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruc
 
 * 32-bit external bus interface, Wishbone b4 compatible
 ([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
-  * [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd) for AXI4-Lite master interface
-* alternative [top entities/wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) providing
-simplified and/or resolved top entity ports for easy system inegration
+  * [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/templates/system/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
+* alternative [top entities/wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/templates) providing
+simplified and/or resolved top entity ports for easy system integration
 * custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
 for tightly-coupled custom co-processor extensions
 
@@ -283,7 +283,7 @@ developed and debugged with open source tooling
 ## Getting Started
 
 This overview provides some *quick links* to the most important sections of the
-[online Data Sheet](https://stnolting.github.io/neorv32) and the 
+[online Data Sheet](https://stnolting.github.io/neorv32) and the
 [online User Guide](https://stnolting.github.io/neorv32/ug).
 
 ### :electric_plug: Hardware Overview

boards/arty-a7-35-test-setup/README.md

@@ -1,7 +1,7 @@
 # NEORV32 Test Setup for the Digilent Arty A7-35 FPGA Board
 
 This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Arty A7-35 board.
-It uses the simplified [`neorv32_test_setup.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) top entity, which is a wrapper for the actual processor
+It uses the simplified [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) top entity, which is a wrapper for the actual processor
 top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs).
 
 * FPGA Board: :books: [Digilent Arty A7-35 FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)
@@ -11,7 +11,7 @@ top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs
 
 ### NEORV32 Configuration
 
-:information_source: See the top entity [`rtl/top_templates/neorv32_test_setup.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) for 
+:information_source: See the top entity [`rtl/templates/processor/neorv32_ProcessorTop_Test.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) for
 configuration and entity details and [`arty_a7_35_test_setup.xdc`](https://github.com/stnolting/neorv32/blob/master/boards/arty-a7-35-test-setup/arty_a7_35_test_setup.xdc)
 for the according FPGA pin mapping.
 
@@ -41,7 +41,7 @@ If not already available, this script will create a `work` folder in this direct
 7. open the "Hardware Manager" (maybe a prompt will ask for that)
 8. click on "Open target/Auto Connect"
 9. click on "Program device" and select `work/neorv32_test_setup.runs/impl_1/neorv32_test_setup.bit`; click "Program"
-10. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: 
+10. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
 19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
 11. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
 and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.

boards/arty-a7-35-test-setup/create_project.tcl

@@ -20,7 +20,7 @@ add_files [glob ./../../rtl/core/*.vhd]
 set_property library neorv32 [get_files [glob ./../../rtl/core/*.vhd]]
 
 # add source file: top entity
-add_files [glob ./../../rtl/top_templates/neorv32_test_setup.vhd]
+add_files [glob ./../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd]
 
 # add source files: simulation-only
 add_files -fileset sim_1 ./../../sim/neorv32_tb.vhd

boards/de0-nano-test-setup/README.md

@@ -1,7 +1,7 @@
 # NEORV32 Test Setup for the Terasic DE0-Nano FPGA Board
 
 This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic DE0-Nano board.
-It uses the simplified [`neorv32_test_setup.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) top entity, which is a wrapper for the actual processor
+It uses the simplified [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) top entity, which is a wrapper for the actual processor
 top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
 
 * FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
@@ -11,7 +11,7 @@ top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs
 
 ### NEORV32 Configuration
 
-:information_source: See the top entity [`rtl/top_templates/neorv32_test_setup.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) for 
+:information_source: See the top entity [`rtl/templates/processor/neorv32_ProcessorTop_Test.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) for
 configuration and entity details and `create_project.tcl` for the according FPGA pin mapping.
 
 * CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors)
@@ -25,7 +25,7 @@ configuration and entity details and `create_project.tcl` for the according FPGA
   * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
   * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
 
-:warning: The default [`neorv32_test_setup.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) top entity
+:warning: The default [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) top entity
 is configured for a 100MHz input clock. Since the on-board oscillator of the DE0-nano board generates a 50MHz clock, the test setup has to be modified.
 This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file
 (in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual
@@ -44,7 +44,7 @@ If not already available, this script will create a `work` folder in this direct
 5. if a "select family" prompt appears select the "Cyclone IV E" family and click OK
 6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream
 7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA
-8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: 
+8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
 19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
 9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
 and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.

boards/de0-nano-test-setup/create_project.tcl

@@ -1,15 +1,15 @@
-# make a local copy of original "./../../rtl/top_templates/neorv32_test_setup.vhd" file
+# make a local copy of original "./../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd" file
 # and modify the default clock frequency: set to 50MHz
-set shell_script "cp -f ./../../rtl/top_templates/neorv32_test_setup.vhd . && sed -i '/CLOCK_FREQUENCY/c\CLOCK_FREQUENCY => 50000000,' neorv32_test_setup.vhd"
+set shell_script "cp -f ./../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd . && sed -i '/CLOCK_FREQUENCY/c\CLOCK_FREQUENCY => 50000000,' neorv32_test_setup.vhd"
 exec sh -c $shell_script
 
 # Copyright (C) 2020  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and any partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
 # Subscription Agreement, the Intel Quartus Prime License Agreement,
 # the Intel FPGA IP License Agreement, or other applicable license
 # agreement, including, without limitation, that your use is for

boards/nexys-a7-test-setup/README.md

@@ -1,13 +1,13 @@
 # NEORV32 Test Setup for the Digilent Nexys A7 and Nexys 4 DDR FPGA Boards
 
 This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Nexys A7 and Nexys 4 DDR boards.
-It uses the simplified [`neorv32_test_setup.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) top entity, which is a wrapper for the actual processor
+It uses the simplified [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) top entity, which is a wrapper for the actual processor
 top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs).
 
-* FPGA Boards: 
+* FPGA Boards:
   * :books: [Digilent Nexys A7 FPGA Boards](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual)
   * :books: [Digilent Nexys 4 DDR FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/reference-manual)
-* FPGAs: 
+* FPGAs:
   * Xilinx Artix-7 `XC7A50TCSG324-1`
   * Xilinx Artix-7 `XC7A100TCSG324-1`
 * Toolchain: Xilinx Vivado (tested with Vivado 2020.2)
@@ -15,7 +15,7 @@ top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs
 
 ### NEORV32 Configuration
 
-:information_source: See the top entity [`rtl/top_templates/neorv32_test_setup.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) for 
+:information_source: See the top entity [`rtl/templates/processor/neorv32_ProcessorTop_Test.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) for
 configuration and entity details and [`nexys_a7_test_setup.xdc`](https://github.com/AWenzel83/neorv32/blob/nexys_a7_example/boards/nexys-a7-test-setup/nexys_a7_test_setup.xdc)
 for the according FPGA pin mapping.
 
@@ -37,15 +37,15 @@ If not already available, this script will create a `work` folder in this direct
 1. start Vivado (in GUI mode)
 2. click on "TCL Console" at the bottom
 3. use the console to naviagte to **this** folder: `cd .../neorv32/boards/nexys-a7-test-setup`
-4. execute the tcl-script according to your board, this will create the actual Vivado project in `work`: 
- * `source create_project_nexys_a7_100.tcl`for a Nexys A7 100 or a Nexys 4 DDR board 
+4. execute the tcl-script according to your board, this will create the actual Vivado project in `work`:
+ * `source create_project_nexys_a7_100.tcl`for a Nexys A7 100 or a Nexys 4 DDR board
  * `source create_project_nexys_a7_50.tcl`for a Nexys A7 50 board
 5. when the Vivado project has openend, click on "Run Implementation"
 6. when the implementation is done create a bitstrem by clicking "Generate Bitstream" (maybe a prompt will ask for that)
 7. open the "Hardware Manager" (maybe a prompt will ask for that)
 8. click on "Open target/Auto Connect"
 9. click on "Program device" and select `work/neorv32_test_setup.runs/impl_1/neorv32_test_setup.bit`; click "Program"
-10. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: 
+10. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
 19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
 11. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
 and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.

boards/nexys-a7-test-setup/create_project_nexys_a7_100.tcl

@@ -20,7 +20,7 @@ add_files [glob ./../../rtl/core/*.vhd]
 set_property library neorv32 [get_files [glob ./../../rtl/core/*.vhd]]
 
 # add source file: top entity
-add_files [glob ./../../rtl/top_templates/neorv32_test_setup.vhd]
+add_files [glob ./../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd]
 
 # add source files: simulation-only
 add_files -fileset sim_1 ./../../sim/neorv32_tb.vhd

boards/nexys-a7-test-setup/create_project_nexys_a7_50.tcl

@@ -20,7 +20,7 @@ add_files [glob ./../../rtl/core/*.vhd]
 set_property library neorv32 [get_files [glob ./../../rtl/core/*.vhd]]
 
 # add source file: top entity
-add_files [glob ./../../rtl/top_templates/neorv32_test_setup.vhd]
+add_files [glob ./../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd]
 
 # add source files: simulation-only
 add_files -fileset sim_1 ./../../sim/neorv32_tb.vhd

docs/datasheet/overview.adoc

@@ -104,16 +104,18 @@ Links in this document are <<_structure,highlighted>>.
 neorv32            - Project home folder
 ├.ci              - Scripts for continuous integration
 ├boards           - Example setups for various FPGA boards
+│├osflow         - Makefile based plumbing for open source EDA tooling (GHDL, yosys, nextpnr, icestorm, etc.)
 ├CHANGELOG.md     - Project change log
 ├docs             - Project documentation
 │├doxygen_build  - Software framework documentation (generated by doxygen)
 │├src_adoc       - AsciiDoc sources for this document
 │├references     - Data sheets and RISC-V specs.
 │└figures        - Figures and logos
+├examples         - Ready-to-use top entities for the supported boards and entrypoint for generating bitstreams
 ├riscv-arch-test  - Port files for the official RISC-V architecture tests
 ├rtl              - VHDL sources
 │├core           - Sources of the CPU & SoC
-│└top_templates  - Alternate/additional top entities/wrappers
+│└templates      - Alternate/additional top entities/wrappers
 ├sim              - Simulation files
 │├ghdl           - Simulation scripts for GHDL
 │├rtl_modules    - Processor modules for simulation-only
@@ -151,7 +153,7 @@ files, like alternative top entities, can be assigned to any library.
 ...................................
 neorv32_top.vhd                      - NEORV32 Processor top entity
 ├neorv32_boot_rom.vhd               - Bootloader ROM
-│└neorv32_bootloader_image.vhd     - Bootloader boot ROM memory image 
+│└neorv32_bootloader_image.vhd     - Bootloader boot ROM memory image
 ├neorv32_busswitch.vhd              - Processor bus switch for CPU buses (I&D)
 ├neorv32_bus_keeper.vhd             - Processor-internal bus monitor
 ├neorv32_icache.vhd                 - Processor-internal instruction cache

docs/datasheet/soc.adoc

@@ -38,7 +38,7 @@ The type of all signals is _std_ulogic_ or _std_ulogic_vector_, respectively.
 
 [TIP]
 A wrapper for the NEORV32 Processor setup providing resolved port signals can be found in
-`rtl/top_templates/neorv32_top_stdlogic.vhd`.
+`rtl/templates/processor/neorv32_ProcessorTop_stdlogic.vhd`.
 
 [cols="<3,^2,^2,<11"]
 [options="header",grid="rows"]
@@ -580,7 +580,7 @@ See sections <<_address_space>> and <<_processor_external_memory_interface_wishb
 [frame="all",grid="none"]
 |======
 | **MEM_EXT_TIMEOUT** | _natural_ | 255
-3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception. Set to 0 to disable auto-timeout. 
+3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception. Set to 0 to disable auto-timeout.
 |======
 
 
@@ -635,7 +635,7 @@ more information.
 [frame="all",grid="none"]
 |======
 | **IO_UART1_EN** | _boolean_ | true
-3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_. 
+3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
 See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
 |======
 

docs/datasheet/soc_wishbone.adoc

@@ -5,7 +5,7 @@
 [cols="<3,<3,<4"]
 [frame="topbot",grid="none"]
 |=======================
-| Hardware source file(s): | neorv32_wishbone.vhd | 
+| Hardware source file(s): | neorv32_wishbone.vhd |
 | Software driver file(s): | none             | _implicitly used_
 | Top entity port:         | `wb_tag_o`  | request tag output (3-bit)
 |                          | `wb_adr_o`  | address output (32-bit)
@@ -25,7 +25,7 @@
 | Configuration constants in VHDL package file `neorv32_package.vhd`: | `wb_pipe_mode_c` | when _false_ (default): classic/standard Wishbone protocol; when _true_: pipelined Wishbone protocol
 |                                                                     | `wb_big_endian_c` | byte-order (Endianness) of external memory interface; true=BIG, false=little (default)
 |                                                                     | `wb_rx_buffer_c` | enable register buffer for RX path (default)
-| CPU interrupts:          | none             | 
+| CPU interrupts:          | none             |
 |=======================
 
 The external memory interface uses the Wishbone interface protocol. The external interface port is available
@@ -82,7 +82,7 @@ processor-incoming ("RX") signals are fully registered. Thus, any access from th
 via Wishbone requires 2 additional clock cycles (at least; depending on device's latency).
 
 If the attached Wishbone network / peripheral already provides output registers or if the Wishbone network is not relevant
-for timing closure, the default buffering of incoming ("RX") data within the gateway can be disabled. 
+for timing closure, the default buffering of incoming ("RX") data within the gateway can be disabled.
 The configuration is done via the `wb_rx_buffer_c` constant in the in the main VHDL package file (`rtl/neorv32_package.vhd`):
 
 [source,vhdl]
@@ -153,7 +153,7 @@ _SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see se
 
 **AXI4-Lite Connectivity**
 
-The AXI4-Lite wrapper (`rtl/top_templates/neorv32_top_axi4lite.vhd`) provides a Wishbone-to-
+The AXI4-Lite wrapper (`rtl/templates/system/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
 AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
 this wrapper are of type _std_logic_ or _std_logic_vector_, respectively.
 
@@ -165,6 +165,4 @@ image::neorv32_axi_soc.png[]
 
 [WARNING]
 Using the auto-termination timeout feature (_MEM_EXT_TIMEOUT_ greater than zero) is **not AXI4 compliant** as the AXI protocol does not support canceling of
-bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/top_templates/neorv32_top_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
-
-
+bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/templates/system/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.

docs/userguide/content.adoc

@@ -143,7 +143,7 @@ provide a field to enter the library name, check out the "properties" menu of th
 already have a design, instantiate this unit into your design and proceed.
 . If you do not have a design yet and just want to check out the NEORV32 – no problem! In this guide
 we will use a simplified top entity, that encapsulated the actual processor top entity: add the
-`rtl/core/top_templates/neorv32_test_setup.vhd` VHDL file to your project too, and
+`rtl/templates/processor/neorv32_ProcessorTop_Test.vhd` VHDL file to your project too, and
 select it as top entity.
 . This test setup provides a minimal test hardware setup:
 

rtl/README.md

@@ -2,10 +2,12 @@
 
 ### [`core`](https://github.com/stnolting/neorv32/tree/master/rtl/core)
 
-This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor. When creating a new synthesis/simulation project make
-sure that all `*.vhd` files from this folder are added to a *new design library* called `neorv32`.
+This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor.
+When creating a new synthesis/simulation project make sure that all `*.vhd` files from this folder are added to a
+*new design library* called `neorv32`.
 
-### [`top_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/top_templates)
+### [templates`](https://github.com/stnolting/neorv32/tree/master/rtl/templates)
 
-Alternative top entities for the NEORV32 Processor. Actually, these *alternative* top entities are wrappers, which instantiate the *real* top entity of
-processor/CPU and provide a different interface.
+Alternative top entities for the NEORV32 Processor.
+Actually, these *alternative* top entities are wrappers, which instantiate the *real* top entity of processor/CPU and
+provide a different interface.

rtl/core/neorv32_top.vhd

@@ -3,7 +3,7 @@
 -- # ********************************************************************************************* #
 -- # This is the top entity of the NEORV32 PROCESSOR. Instantiate this unit in your own project    #
 -- # and define all the configuration generics according to your needs. Alternatively, you can use #
--- # one of the alternative top entities provided in the "rtl/top_templates" folder.               #
+-- # one of the alternative top entities provided in the "rtl/templates" folder.                   #
 -- #                                                                                               #
 -- # Check out the processor's documentation for more information.                                 #
 -- # ********************************************************************************************* #
@@ -808,7 +808,7 @@ begin
   if (IO_CFS_EN = true) generate
     neorv32_cfs_inst: neorv32_cfs
     generic map (
-      CFS_CONFIG   => IO_CFS_CONFIG,  -- custom CFS configuration generic 
+      CFS_CONFIG   => IO_CFS_CONFIG,  -- custom CFS configuration generic
       CFS_IN_SIZE  => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
       CFS_OUT_SIZE => IO_CFS_OUT_SIZE -- size of CFS output conduit in bits
     )

sim/ghdl/ghdl_sim.sh

@@ -26,9 +26,9 @@ echo ""
 
 # List files
 #echo "Simulation source files:"
-#ls -l simrtl/core
+#ls -l rtl/core
 #ls -l sim
-#ls -l rtl/top_templates
+#ls -l rtl/templates
 #echo ""
 
 # Just a hint
@@ -37,7 +37,8 @@ echo ""
 
 # Analyse sources; libs and images at first!
 ghdl -i --work=neorv32 rtl/core/*.vhd
-ghdl -i --work=neorv32 rtl/top_templates/*.vhd
+ghdl -i --work=neorv32 rtl/templates/processor/*.vhd
+ghdl -i --work=neorv32 rtl/templates/system/*.vhd
 ghdl -i --work=neorv32 sim/*.vhd
 
 # Prepare simulation output files for UART0 and UART 1