github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 14:17:51 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[AXI wrapper] connect external MTIME IRQ

Browse source
This commit is contained in:
stnolting 2023-09-15 20:37:36 +02:00
parent f0a047886c
commit 8c90c81388
1 changed files with 3 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
View file

@ -298,6 +298,7 @@ architecture neorv32_SystemTop_axi4lite_rtl of neorv32_SystemTop_axi4lite is
--
signal xirq_i_int : std_ulogic_vector(31 downto 0);
--
signal mtime_irq_i_int : std_ulogic;
signal msw_irq_i_int : std_ulogic;
signal mext_irq_i_int : std_ulogic;
@ -496,7 +497,7 @@ begin
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
xirq_i => xirq_i_int, -- IRQ channels
-- CPU Interrupts --
mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false
mtime_irq_i => mtime_irq_i_int, -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i => msw_irq_i_int, -- machine software interrupt
mext_irq_i => mext_irq_i_int -- machine external interrupt
);
@ -554,6 +555,7 @@ begin
xirq_i_int <= std_ulogic_vector(xirq_i);
mtime_irq_i_int <= std_ulogic(mtime_irq_i);
msw_irq_i_int <= std_ulogic(msw_irq_i);
mext_irq_i_int <= std_ulogic(mext_irq_i);