github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-23 21:57:33 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

[top] update/add XIP generics

Browse source
This commit is contained in:
stnolting 2024-02-09 11:50:39 +01:00
parent 0e08dc328c
commit 8cfb56f286
7 changed files with 151 additions and 114 deletions
Download patch file Download diff file Expand all files Collapse all files

90
rtl/core/neorv32_package.vhd
View file

@ -750,60 +750,65 @@ package neorv32_package is
generic (
-- General --
CLOCK_FREQUENCY : natural;
CLOCK_GATING_EN : boolean := false;
CLOCK_GATING_EN : boolean := false;
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000";
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000";
INT_BOOTLOADER_EN : boolean := false;
INT_BOOTLOADER_EN : boolean := false;
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN : boolean := false;
DM_LEGACY_MODE : boolean := false;
ON_CHIP_DEBUGGER_EN : boolean := false;
DM_LEGACY_MODE : boolean := false;
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false;
CPU_EXTENSION_RISCV_B : boolean := false;
CPU_EXTENSION_RISCV_C : boolean := false;
CPU_EXTENSION_RISCV_E : boolean := false;
CPU_EXTENSION_RISCV_M : boolean := false;
CPU_EXTENSION_RISCV_U : boolean := false;
CPU_EXTENSION_RISCV_Zfinx : boolean := false;
CPU_EXTENSION_RISCV_Zicntr : boolean := true;
CPU_EXTENSION_RISCV_Zicond : boolean := false;
CPU_EXTENSION_RISCV_Zihpm : boolean := false;
CPU_EXTENSION_RISCV_Zmmul : boolean := false;
CPU_EXTENSION_RISCV_Zxcfu : boolean := false;
CPU_EXTENSION_RISCV_A : boolean := false;
CPU_EXTENSION_RISCV_B : boolean := false;
CPU_EXTENSION_RISCV_C : boolean := false;
CPU_EXTENSION_RISCV_E : boolean := false;
CPU_EXTENSION_RISCV_M : boolean := false;
CPU_EXTENSION_RISCV_U : boolean := false;
CPU_EXTENSION_RISCV_Zfinx : boolean := false;
CPU_EXTENSION_RISCV_Zicntr : boolean := true;
CPU_EXTENSION_RISCV_Zicond : boolean := false;
CPU_EXTENSION_RISCV_Zihpm : boolean := false;
CPU_EXTENSION_RISCV_Zmmul : boolean := false;
CPU_EXTENSION_RISCV_Zxcfu : boolean := false;
-- Tuning Options --
FAST_MUL_EN : boolean := false;
FAST_SHIFT_EN : boolean := false;
REGFILE_HW_RST : boolean := false;
FAST_MUL_EN : boolean := false;
FAST_SHIFT_EN : boolean := false;
REGFILE_HW_RST : boolean := false;
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural range 0 to 16 := 0;
PMP_MIN_GRANULARITY : natural := 4;
PMP_NUM_REGIONS : natural range 0 to 16 := 0;
PMP_MIN_GRANULARITY : natural := 4;
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural range 0 to 13 := 0;
HPM_CNT_WIDTH : natural range 0 to 64 := 40;
HPM_NUM_CNTS : natural range 0 to 13 := 0;
HPM_CNT_WIDTH : natural range 0 to 64 := 40;
-- Atomic Memory Access - Reservation Set Granularity --
AMO_RVS_GRANULARITY : natural := 4;
AMO_RVS_GRANULARITY : natural := 4;
-- Internal Instruction memory (IMEM) --
MEM_INT_IMEM_EN : boolean := false;
MEM_INT_IMEM_SIZE : natural := 16*1024;
MEM_INT_IMEM_EN : boolean := false;
MEM_INT_IMEM_SIZE : natural := 16*1024;
-- Internal Data memory (DMEM) --
MEM_INT_DMEM_EN : boolean := false;
MEM_INT_DMEM_SIZE : natural := 8*1024;
MEM_INT_DMEM_EN : boolean := false;
MEM_INT_DMEM_SIZE : natural := 8*1024;
-- Internal Instruction Cache (iCACHE) --
ICACHE_EN : boolean := false;
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
ICACHE_ASSOCIATIVITY : natural range 1 to 2 := 1;
ICACHE_EN : boolean := false;
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
ICACHE_ASSOCIATIVITY : natural range 1 to 2 := 1;
-- Internal Data Cache (dCACHE) --
DCACHE_EN : boolean := false;
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
DCACHE_EN : boolean := false;
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
-- External memory interface (WISHBONE) --
MEM_EXT_EN : boolean := false;
MEM_EXT_TIMEOUT : natural := 255;
MEM_EXT_PIPE_MODE : boolean := false;
MEM_EXT_BIG_ENDIAN : boolean := false;
MEM_EXT_ASYNC_RX : boolean := false;
MEM_EXT_ASYNC_TX : boolean := false;
MEM_EXT_EN : boolean := false;
MEM_EXT_TIMEOUT : natural := 255;
MEM_EXT_PIPE_MODE : boolean := false;
MEM_EXT_BIG_ENDIAN : boolean := false;
MEM_EXT_ASYNC_RX : boolean := false;
MEM_EXT_ASYNC_TX : boolean := false;
-- Execute in-place module (XIP) --
XIP_EN : boolean := false;
XIP_CACHE_EN : boolean := false;
XIP_CACHE_NUM_BLOCKS : natural range 1 to 256 := 8;
XIP_CACHE_BLOCK_SIZE : natural range 1 to 2**16 := 256;
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural range 0 to 32 := 0;
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff";
@ -833,7 +838,6 @@ package neorv32_package is
IO_NEOLED_EN : boolean := false;
IO_NEOLED_TX_FIFO : natural range 1 to 2**15 := 1;
IO_GPTMR_EN : boolean := false;
IO_XIP_EN : boolean := false;
IO_ONEWIRE_EN : boolean := false;
IO_DMA_EN : boolean := false;
IO_SLINK_EN : boolean := false;
@ -872,7 +876,7 @@ package neorv32_package is
-- Advanced memory control signals --
fence_o : out std_ulogic;
fencei_o : out std_ulogic;
-- XIP (execute in-place via SPI) signals (available if IO_XIP_EN = true) --
-- XIP (execute in-place via SPI) signals (available if XIP_EN = true) --
xip_csn_o : out std_ulogic;
xip_clk_o : out std_ulogic;
xip_dat_i : in std_ulogic := 'L';

4
rtl/core/neorv32_sysinfo.vhd
View file

@ -84,7 +84,7 @@ entity neorv32_sysinfo is
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_EN : boolean; -- implement external interrupts controller (XIRQ)?
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean; -- implement execute in place module (XIP)?
XIP_EN : boolean; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean; -- implement 1-wire interface (ONEWIRE)?
IO_DMA_EN : boolean; -- implement direct memory access controller (DMA)?
IO_SLINK_EN : boolean; -- implement stream link interface (SLINK)?
@ -151,7 +151,7 @@ begin
sysinfo(2)(26) <= '1' when IO_NEOLED_EN else '0'; -- NeoPixel-compatible smart LED interface (NEOLED) implemented?
sysinfo(2)(27) <= '1' when IO_XIRQ_EN else '0'; -- external interrupt controller (XIRQ) implemented?
sysinfo(2)(28) <= '1' when IO_GPTMR_EN else '0'; -- general purpose timer (GPTMR) implemented?
sysinfo(2)(29) <= '1' when IO_XIP_EN else '0'; -- execute in place module (XIP) implemented?
sysinfo(2)(29) <= '1' when XIP_EN else '0'; -- execute in place module (XIP) implemented?
sysinfo(2)(30) <= '1' when IO_ONEWIRE_EN else '0'; -- 1-wire interface (ONEWIRE) implemented?
sysinfo(2)(31) <= '1' when ON_CHIP_DEBUGGER_EN else '0'; -- on-chip debugger implemented?

110
rtl/core/neorv32_top.vhd
View file

@ -47,71 +47,77 @@ entity neorv32_top is
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
CLOCK_GATING_EN : boolean := false; -- enable clock gating when in sleep mode
CLOCK_GATING_EN : boolean := false; -- enable clock gating when in sleep mode
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
CPU_EXTENSION_RISCV_Zicond : boolean := false; -- implement integer conditional operations?
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
CPU_EXTENSION_RISCV_Zicond : boolean := false; -- implement integer conditional operations?
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
-- Tuning Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
REGFILE_HW_RST : boolean := false; -- implement full hardware reset for register file
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
REGFILE_HW_RST : boolean := false; -- implement full hardware reset for register file
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural range 0 to 16 := 0; -- number of regions (0..16)
PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
PMP_NUM_REGIONS : natural range 0 to 16 := 0; -- number of regions (0..16)
PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural range 0 to 13 := 0; -- number of implemented HPM counters (0..13)
HPM_CNT_WIDTH : natural range 0 to 64 := 40; -- total size of HPM counters (0..64)
HPM_NUM_CNTS : natural range 0 to 13 := 0; -- number of implemented HPM counters (0..13)
HPM_CNT_WIDTH : natural range 0 to 64 := 40; -- total size of HPM counters (0..64)
-- Atomic Memory Access - Reservation Set Granularity --
AMO_RVS_GRANULARITY : natural := 4; -- size in bytes, has to be a power of 2, min 4
AMO_RVS_GRANULARITY : natural := 4; -- size in bytes, has to be a power of 2, min 4
-- Internal Instruction memory (IMEM) --
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes (use a power of 2)
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes (use a power of 2)
-- Internal Data memory (DMEM) --
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes (use a power of 2)
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes (use a power of 2)
-- Internal Instruction Cache (iCACHE) --
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural range 1 to 2 := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural range 1 to 2 := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- Internal Data Cache (dCACHE) --
DCACHE_EN : boolean := false; -- implement data cache
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
DCACHE_EN : boolean := false; -- implement data cache
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
-- External memory interface (WISHBONE) --
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false
MEM_EXT_ASYNC_TX : boolean := false; -- use register buffer for TX data when false
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false
MEM_EXT_ASYNC_TX : boolean := false; -- use register buffer for TX data when false
-- Execute in-place module (XIP) --
XIP_EN : boolean := false; -- implement execute in place module (XIP)?
XIP_CACHE_EN : boolean := false; -- implement XIP cache?
XIP_CACHE_NUM_BLOCKS : natural range 1 to 256 := 8; -- number of blocks (min 1), has to be a power of 2
XIP_CACHE_BLOCK_SIZE : natural range 1 to 2**16 := 256; -- block size in bytes (min 4), has to be a power of 2
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural range 0 to 32 := 0; -- number of external IRQ channels (0..32)
@ -143,7 +149,6 @@ entity neorv32_top is
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural range 1 to 2**15 := 1; -- NEOLED FIFO depth, has to be a power of two, min 1
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)?
IO_DMA_EN : boolean := false; -- implement direct memory access controller (DMA)?
IO_SLINK_EN : boolean := false; -- implement stream link interface (SLINK)?
@ -187,7 +192,7 @@ entity neorv32_top is
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
-- XIP (execute in place via SPI) signals (available if XIP_EN = true) --
xip_csn_o : out std_ulogic; -- chip-select, low-active
xip_clk_o : out std_ulogic; -- serial clock
xip_dat_i : in std_ulogic := 'L'; -- device data input
@ -380,7 +385,7 @@ begin
cond_sel_string_f(IO_NEOLED_EN, "NEOLED ", "") &
cond_sel_string_f(io_xirq_en_c, "XIRQ ", "") &
cond_sel_string_f(IO_GPTMR_EN, "GPTMR ", "") &
cond_sel_string_f(IO_XIP_EN, "XIP ", "") &
cond_sel_string_f(XIP_EN, "XIP ", "") &
cond_sel_string_f(IO_ONEWIRE_EN, "ONEWIRE ", "") &
cond_sel_string_f(IO_DMA_EN, "DMA ", "") &
cond_sel_string_f(IO_SLINK_EN, "SLINK ", "") &
@ -762,7 +767,7 @@ begin
DMEM_BASE => mem_dmem_base_c,
DMEM_SIZE => dmem_size_c,
-- XIP port --
XIP_ENABLE => IO_XIP_EN,
XIP_ENABLE => XIP_EN,
XIP_BASE => mem_xip_base_c,
XIP_SIZE => mem_xip_size_c,
-- BOOT ROM port --
@ -872,8 +877,13 @@ begin
-- Execute In Place Module (XIP) ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_xip_inst_true:
if (IO_XIP_EN = true) generate
if (XIP_EN = true) generate
neorv32_xip_inst: entity neorv32.neorv32_xip
generic map (
XIP_CACHE_EN => XIP_CACHE_EN,
XIP_CACHE_NUM_BLOCKS => XIP_CACHE_NUM_BLOCKS,
XIP_CACHE_BLOCK_SIZE => XIP_CACHE_BLOCK_SIZE
)
port map (
-- global control --
clk_i => clk_i,
@ -892,7 +902,7 @@ begin
end generate;
neorv32_xip_inst_false:
if (IO_XIP_EN = false) generate
if (XIP_EN = false) generate
iodev_rsp(IODEV_XIP) <= rsp_terminate_c;
xip_rsp <= rsp_terminate_c;
cg_en.xip <= '0';
@ -976,7 +986,7 @@ begin
DEV_13_EN => IO_ONEWIRE_EN, DEV_13_BASE => base_io_onewire_c,
DEV_14_EN => IO_GPTMR_EN, DEV_14_BASE => base_io_gptmr_c,
DEV_15_EN => io_pwm_en_c, DEV_15_BASE => base_io_pwm_c,
DEV_16_EN => IO_XIP_EN, DEV_16_BASE => base_io_xip_c,
DEV_16_EN => XIP_EN, DEV_16_BASE => base_io_xip_c,
DEV_17_EN => IO_CRC_EN, DEV_17_BASE => base_io_crc_c,
DEV_18_EN => IO_DMA_EN, DEV_18_BASE => base_io_dma_c,
DEV_19_EN => IO_SLINK_EN, DEV_19_BASE => base_io_slink_c,
@ -1047,7 +1057,7 @@ begin
-- -------------------------------------------------------------------------------------------
neorv32_sdi_inst_true:
if (IO_SDI_EN = true) generate
neorv32_SDI_inst: entity neorv32.neorv32_sdi
neorv32_sdi_inst: entity neorv32.neorv32_sdi
generic map (
RTX_FIFO => IO_SDI_FIFO
)
@ -1562,7 +1572,7 @@ begin
IO_NEOLED_EN => IO_NEOLED_EN,
IO_XIRQ_EN => io_xirq_en_c,
IO_GPTMR_EN => IO_GPTMR_EN,
IO_XIP_EN => IO_XIP_EN,
XIP_EN => XIP_EN,
IO_ONEWIRE_EN => IO_ONEWIRE_EN,
IO_DMA_EN => IO_DMA_EN,
IO_SLINK_EN => IO_SLINK_EN,

24
rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd
View file

@ -1,12 +1,12 @@
-- #################################################################################################
-- # << NEORV32 - Processor Top Entity with AvalonMM Compatible Master Interface >> #
-- # << NEORV32 - Processor Top Entity with AvalonMM Compatible Host Interface >> #
-- # ********************************************************************************************* #
-- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" #
-- # are trademarks of Intel #
-- # (c) "AvalonMM", "Qsys", "MegaWizard" and "Platform Designer" are trademarks of Intel corp. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
@ -31,8 +31,6 @@
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
@ -96,6 +94,12 @@ entity neorv32_top_avalonmm is
DCACHE_NUM_BLOCKS : natural := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
-- Execute in-place module (XIP) --
XIP_EN : boolean := false; -- implement execute in place module (XIP)?
XIP_CACHE_EN : boolean := false; -- implement XIP cache?
XIP_CACHE_NUM_BLOCKS : natural range 1 to 256 := 8; -- number of blocks (min 1), has to be a power of 2
XIP_CACHE_BLOCK_SIZE : natural range 1 to 2**16 := 256; -- block size in bytes (min 4), has to be a power of 2
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
@ -124,7 +128,6 @@ entity neorv32_top_avalonmm is
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean := false -- implement 1-wire interface (ONEWIRE)?
);
port (
@ -287,6 +290,12 @@ begin
MEM_EXT_ASYNC_RX => false,
MEM_EXT_ASYNC_TX => false,
-- Execute in-place module (XIP) --
XIP_EN => XIP_EN,
XIP_CACHE_EN => XIP_CACHE_EN,
XIP_CACHE_NUM_BLOCKS => XIP_CACHE_NUM_BLOCKS,
XIP_CACHE_BLOCK_SIZE => XIP_CACHE_BLOCK_SIZE,
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH => XIRQ_NUM_CH,
XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE,
@ -315,7 +324,6 @@ begin
IO_NEOLED_EN => IO_NEOLED_EN,
IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO,
IO_GPTMR_EN => IO_GPTMR_EN,
IO_XIP_EN => IO_XIP_EN,
IO_ONEWIRE_EN => IO_ONEWIRE_EN
)
port map (

21
rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
View file

@ -1,11 +1,12 @@
-- #################################################################################################
-- # << NEORV32 - Processor Top Entity with AXI4-Lite Compatible Master Interface >> #
-- # << NEORV32 - Processor Top Entity with AXI4-Lite Compatible Host Interface >> #
-- # ********************************************************************************************* #
-- # (c) "AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc. #
-- # (c) "AXI", "AXI4" and "AXI4-Lite" are trademarks of ARM Holdings plc. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
@ -30,8 +31,6 @@
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
@ -92,6 +91,11 @@ entity neorv32_SystemTop_axi4lite is
DCACHE_EN : boolean := false; -- implement data cache
DCACHE_NUM_BLOCKS : natural := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
-- Execute in-place module (XIP) --
XIP_EN : boolean := false; -- implement execute in place module (XIP)?
XIP_CACHE_EN : boolean := false; -- implement XIP cache?
XIP_CACHE_NUM_BLOCKS : natural range 1 to 256 := 8; -- number of blocks (min 1), has to be a power of 2
XIP_CACHE_BLOCK_SIZE : natural range 1 to 2**16 := 256; -- block size in bytes (min 4), has to be a power of 2
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge
@ -121,7 +125,6 @@ entity neorv32_SystemTop_axi4lite is
IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)?
IO_DMA_EN : boolean := false; -- implement direct memory access controller (DMA)?
IO_SLINK_EN : boolean := false; -- implement stream link interface (SLINK)?
@ -386,6 +389,11 @@ begin
MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX => false, -- use register buffer for RX data when false
MEM_EXT_ASYNC_TX => false, -- use register buffer for TX data when false
-- Execute in-place module (XIP) --
XIP_EN => XIP_EN, -- implement execute in place module (XIP)?
XIP_CACHE_EN => XIP_CACHE_EN, -- implement XIP cache?
XIP_CACHE_NUM_BLOCKS => XIP_CACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2
XIP_CACHE_BLOCK_SIZE => XIP_CACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE_INT, -- trigger type: 0=level, 1=edge
@ -415,7 +423,6 @@ begin
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)?
IO_XIP_EN => IO_XIP_EN, -- implement execute in place module (XIP)?
IO_ONEWIRE_EN => IO_ONEWIRE_EN, -- implement 1-wire interface (ONEWIRE)?
IO_DMA_EN => IO_DMA_EN, -- implement direct memory access controller (DMA)?
IO_SLINK_EN => IO_SLINK_EN, -- implement stream link interface (SLINK)?

8
sim/neorv32_tb.vhd
View file

@ -267,6 +267,11 @@ begin
MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX => true, -- use register buffer for RX data when false
MEM_EXT_ASYNC_TX => true, -- use register buffer for TX data when false
-- Execute in-place module (XIP) --
XIP_EN => true, -- implement execute in place module (XIP)?
XIP_CACHE_EN => true, -- implement XIP cache?
XIP_CACHE_NUM_BLOCKS => 4, -- number of blocks (min 1), has to be a power of 2
XIP_CACHE_BLOCK_SIZE => 256, -- block size in bytes (min 4), has to be a power of 2
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH => 32, -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE => (others => '1'), -- trigger type: 0=level, 1=edge
@ -296,7 +301,6 @@ begin
IO_NEOLED_EN => true, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO => 8, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
IO_GPTMR_EN => true, -- implement general purpose timer (GPTMR)?
IO_XIP_EN => true, -- implement execute in place module (XIP)?
IO_ONEWIRE_EN => true, -- implement 1-wire interface (ONEWIRE)?
IO_DMA_EN => true, -- implement direct memory access controller (DMA)?
IO_SLINK_EN => true, -- implement stream link interface (SLINK)?
@ -335,7 +339,7 @@ begin
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o => open, -- indicates an executed FENCE operation
fencei_o => open, -- indicates an executed FENCEI operation
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
-- XIP (execute in place via SPI) signals (available if XIP_EN = true) --
xip_csn_o => open, -- chip-select, low-active
xip_clk_o => open, -- serial clock
xip_dat_i => '1', -- device data input

8
sim/simple/neorv32_tb.simple.vhd
View file

@ -215,6 +215,11 @@ begin
MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX => false, -- use register buffer for RX data when false
MEM_EXT_ASYNC_TX => false, -- use register buffer for TX data when false
-- Execute in-place module (XIP) --
XIP_EN => true, -- implement execute in place module (XIP)?
XIP_CACHE_EN => true, -- implement XIP cache?
XIP_CACHE_NUM_BLOCKS => 4, -- number of blocks (min 1), has to be a power of 2
XIP_CACHE_BLOCK_SIZE => 256, -- block size in bytes (min 4), has to be a power of 2
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH => 32, -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE => (others => '1'), -- trigger type: 0=level, 1=edge
@ -244,7 +249,6 @@ begin
IO_NEOLED_EN => true, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO => 8, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
IO_GPTMR_EN => true, -- implement general purpose timer (GPTMR)?
IO_XIP_EN => true, -- implement execute in place module (XIP)?
IO_ONEWIRE_EN => true, -- implement 1-wire interface (ONEWIRE)?
IO_DMA_EN => true, -- implement direct memory access controller (DMA)?
IO_SLINK_EN => true, -- implement stream link interface (SLINK)?
@ -283,7 +287,7 @@ begin
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o => open, -- indicates an executed FENCE operation
fencei_o => open, -- indicates an executed FENCEI operation
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
-- XIP (execute in place via SPI) signals (available if XIP_EN = true) --
xip_csn_o => open, -- chip-select, low-active
xip_clk_o => open, -- serial clock
xip_dat_i => '0', -- device data input