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add emulation library for unsupported AMO instructions

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-> based on LR/SC pairs
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stnolting 2023-07-22 07:42:06 +02:00
parent f0f1b71d34
commit 8e629db18b
5 changed files with 365 additions and 2 deletions
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14
docs/datasheet/cpu.adoc
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@ -50,7 +50,8 @@ will raise an exception to allow a _software-based_ emulation provided by the ap
[IMPORTANT]
The NEORV32 <<_a_isa_extension>> only supports the load-reservate (LR) and store-conditional (SR) instructions.
The remaining read-modify-write operations are not supported. However, these missing instructions can
be emulated by using LR/SC pairs.
be emulated. The NEORV32 <<_core_libraries>> provide an emulation wrapper for the missing AMO/read-modify-write
instructions that is based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
<<<
@ -297,6 +298,11 @@ only includes the _load-reservate_ (`lr.w`) and _store-conditional_ (`sc.w`) ins
instructions (like `amoswap`) are **not supported**. However, these missing instructions can be emulated using the
LR and SC operations.
.AMO Emulation
[NOTE]
The NEORV32 <<_core_libraries>> provide an emulation wrapper for the missing AMO/read-modify-write instructions that is
based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
Atomic instructions allow to notify an application if a certain memory location has been altered by another instance
(like another process running on the same CPU or a DMA access). Hence, they can be used to implement synchronization
mechanisms like mutexes and semaphores).
@ -865,6 +871,12 @@ load/store bus transactions but with the `rvso` ("reservation set operation") si
[NOTE]
See section <<_address_space>> / <<_reservation_set_controller>> for more information.
.Read-Modify-Write Operations
[IMPORTANT]
Read-modify-write operations (line an atomic swap / `amoswap.w`) are **not** supported. However, the NEORV32
<<_core_libraries>> provide an emulation wrapper for those unsupported instructions that is
based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
The figure below shows three exemplary bus accesses. For easier understanding the current state of the reservation set
is added as `rvs_valid` signal.

3
docs/datasheet/software.adoc
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@ -86,6 +86,7 @@ The NEORV32 project provides a set of pre-defined C libraries that allow an easy
| `neorv32_cfs.c` | `neorv32_cfs.h` | <<_custom_functions_subsystem_cfs>> HAL
| `neorv32_crc.c` | `neorv32_crc.h` | <<_cyclic_redundancy_check_crc>> HAL
| `neorv32_cpu.c` | `neorv32_cpu.h` | <<_neorv32_central_processing_unit_cpu>> HAL
| `neorv32_cpu_amo.c` | `neorv32_cpu_amo.h` | Emulation functions for the read-modify-write <<_a_isa_extension>> instructions
| | `neorv32_cpu_csr.h` | <<_control_and_status_registers_csrs>> definitions
| `neorv32_cpu_cfu.c` | `neorv32_cpu_cfu.h` | <<_custom_functions_unit_cfu>> HAL
| - | `neorv32_dm.h` | <<_debug_module_dm>> HAL
@ -108,7 +109,7 @@ The NEORV32 project provides a set of pre-defined C libraries that allow an easy
| `neorv32_wdt.c` | `neorv32_wdt.h` | <<_watchdog_timer_wdt>> HAL
| `neorv32_xip.c` | `neorv32_xip.h` | <<_execute_in_place_module_xip>> HAL
| `neorv32_xirq.c` | `neorv32_xirq.h` | <<_external_interrupt_controller_xirq>> HAL
| `syscalls.c` | - | Newlib "system calls"
| `syscalls.c` | - | Newlib "system calls" (stubs)
| - | `legacy.h` | Backwards compatibility wrappers and functions (do not use for new designs)
|=======================

1
sw/lib/include/neorv32.h
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@ -232,6 +232,7 @@ enum NEORV32_CLOCK_PRSC_enum {
// cpu core
#include "neorv32_cpu.h"
#include "neorv32_cpu_amo.h"
#include "neorv32_cpu_csr.h"
#include "neorv32_cpu_cfu.h"

55
sw/lib/include/neorv32_cpu_amo.h Normal file
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@ -0,0 +1,55 @@
// #################################################################################################
// # << NEORV32: neorv32_amo.h - CPU Core - Atomic Memory Access Emulation Functions >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
/**********************************************************************//**
* @file neorv32_cpu_amo.h
* @brief Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - header file.
**************************************************************************/
#ifndef neorv32_cpu_amo_h
#define neorv32_cpu_amo_h
// prototypes
uint32_t neorv32_cpu_amoswapw(uint32_t addr, uint32_t wdata);
uint32_t neorv32_cpu_amoaddw(uint32_t addr, uint32_t wdata);
uint32_t neorv32_cpu_amoandw(uint32_t addr, uint32_t wdata);
uint32_t neorv32_cpu_amoorw(uint32_t addr, uint32_t wdata);
uint32_t neorv32_cpu_amoxorw(uint32_t addr, uint32_t wdata);
int32_t neorv32_cpu_amomaxw(uint32_t addr, int32_t wdata);
uint32_t neorv32_cpu_amomaxuw(uint32_t addr, uint32_t wdata);
int32_t neorv32_cpu_amominw(uint32_t addr, int32_t wdata);
uint32_t neorv32_cpu_amominuw(uint32_t addr, uint32_t wdata);
#endif // neorv32_cpu_amo_h

294
sw/lib/source/neorv32_cpu_amo.c Normal file
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@ -0,0 +1,294 @@
// #################################################################################################
// # << NEORV32: neorv32_amo.c - CPU Core - Atomic Memory Access Emulation Functions >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
/**********************************************************************//**
* @file neorv32_cpu_amo.c
* @brief Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - source file.
**************************************************************************/
#include "neorv32.h"
#include "neorv32_cpu_amo.h"
/**********************************************************************//**
* MIN/MAX helpers.
**************************************************************************/
/**@{*/
static inline int32_t MAX(int32_t a, int32_t b) { return((a) > (b) ? a : b); }
static inline int32_t MIN(int32_t a, int32_t b) { return((a) < (b) ? a : b); }
static inline int32_t MAXU(uint32_t a, uint32_t b) { return((a) > (b) ? a : b); }
static inline int32_t MINU(uint32_t a, uint32_t b) { return((a) < (b) ? a : b); }
/**@}*/
/**********************************************************************//**
* Atomic SWAP (AMOSWAP.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically stored to address (32-bit).
* @return Pre-operation data loaded from address (32-bit)
**************************************************************************/
uint32_t neorv32_cpu_amoswapw(uint32_t addr, uint32_t wdata) {
uint32_t rdata;
uint32_t status;
while(1) {
rdata = neorv32_cpu_load_reservate_word(addr);
status = neorv32_cpu_store_conditional_word(addr, wdata);
if (status == 0) {
break;
}
}
return rdata;
}
/**********************************************************************//**
* Atomic ADD (AMOADD.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically added to original data at address (32-bit).
* @return Pre-operation data loaded from address (32-bit)
**************************************************************************/
uint32_t neorv32_cpu_amoaddw(uint32_t addr, uint32_t wdata) {
uint32_t rdata;
uint32_t tmp;
uint32_t status;
while(1) {
rdata = neorv32_cpu_load_reservate_word(addr);
tmp = rdata + wdata;
status = neorv32_cpu_store_conditional_word(addr, tmp);
if (status == 0) {
break;
}
}
return rdata;
}
/**********************************************************************//**
* Atomic AND (AMOAND.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically AND-ed with original data at address (32-bit).
* @return Pre-operation data loaded from address (32-bit)
**************************************************************************/
uint32_t neorv32_cpu_amoandw(uint32_t addr, uint32_t wdata) {
uint32_t rdata;
uint32_t tmp;
uint32_t status;
while(1) {
rdata = neorv32_cpu_load_reservate_word(addr);
tmp = rdata & wdata;
status = neorv32_cpu_store_conditional_word(addr, tmp);
if (status == 0) {
break;
}
}
return rdata;
}
/**********************************************************************//**
* Atomic OR (AMOOR.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically OR-ed with original data at address (32-bit).
* @return Pre-operation data loaded from address (32-bit)
**************************************************************************/
uint32_t neorv32_cpu_amoorw(uint32_t addr, uint32_t wdata) {
uint32_t rdata;
uint32_t tmp;
uint32_t status;
while(1) {
rdata = neorv32_cpu_load_reservate_word(addr);
tmp = rdata | wdata;
status = neorv32_cpu_store_conditional_word(addr, tmp);
if (status == 0) {
break;
}
}
return rdata;
}
/**********************************************************************//**
* Atomic XOR (AMOXOR.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically XOR-ed with original data at address (32-bit).
* @return Pre-operation data loaded from address (32-bit)
**************************************************************************/
uint32_t neorv32_cpu_amoxorw(uint32_t addr, uint32_t wdata) {
uint32_t rdata;
uint32_t tmp;
uint32_t status;
while(1) {
rdata = neorv32_cpu_load_reservate_word(addr);
tmp = rdata ^ wdata;
status = neorv32_cpu_store_conditional_word(addr, tmp);
if (status == 0) {
break;
}
}
return rdata;
}
/**********************************************************************//**
* Atomic signed MAX (AMOMAX.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically MAX-ed with original data at address (signed 32-bit).
* @return Pre-operation data loaded from address (signed 32-bit)
**************************************************************************/
int32_t neorv32_cpu_amomaxw(uint32_t addr, int32_t wdata) {
int32_t rdata;
int32_t tmp;
uint32_t status;
while(1) {
rdata = (int32_t)neorv32_cpu_load_reservate_word(addr);
tmp = MAX(rdata, wdata);
status = neorv32_cpu_store_conditional_word(addr, tmp);
if (status == 0) {
break;
}
}
return rdata;
}
/**********************************************************************//**
* Atomic unsigned MAX (AMOMAXU.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically MAX-ed with original data at address (unsigned 32-bit).
* @return Pre-operation data loaded from address (unsigned 32-bit)
**************************************************************************/
uint32_t neorv32_cpu_amomaxuw(uint32_t addr, uint32_t wdata) {
uint32_t rdata;
uint32_t tmp;
uint32_t status;
while(1) {
rdata = (uint32_t)neorv32_cpu_load_reservate_word(addr);
tmp = MAXU(rdata, wdata);
status = neorv32_cpu_store_conditional_word(addr, tmp);
if (status == 0) {
break;
}
}
return rdata;
}
/**********************************************************************//**
* Atomic signed MIN (AMOMIN.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically MAX-ed with original data at address (signed 32-bit).
* @return Pre-operation data loaded from address (signed 32-bit)
**************************************************************************/
int32_t neorv32_cpu_amominw(uint32_t addr, int32_t wdata) {
int32_t rdata;
int32_t tmp;
uint32_t status;
while(1) {
rdata = (int32_t)neorv32_cpu_load_reservate_word(addr);
tmp = MIN(rdata, wdata);
status = neorv32_cpu_store_conditional_word(addr, tmp);
if (status == 0) {
break;
}
}
return rdata;
}
/**********************************************************************//**
* Atomic unsigned MIN (AMOMINU.W).
* @note This function requires the CPU A ISA extension.
*
* @param[in] addr 32-bit memory address, word-aligned.
* @param[in] wdata Data word to be atomically MAX-ed with original data at address (unsigned 32-bit).
* @return Pre-operation data loaded from address (unsigned 32-bit)
**************************************************************************/
uint32_t neorv32_cpu_amominuw(uint32_t addr, uint32_t wdata) {
uint32_t rdata;
uint32_t tmp;
uint32_t status;
while(1) {
rdata = (uint32_t)neorv32_cpu_load_reservate_word(addr);
tmp = MINU(rdata, wdata);
status = neorv32_cpu_store_conditional_word(addr, tmp);
if (status == 0) {
break;
}
}
return rdata;
}