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[docs] remove trailing spaces

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stnolting 2024-03-23 21:22:56 +01:00
parent 336acae768
commit 8eecf78636
2 changed files with 4 additions and 4 deletions
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3
docs/datasheet/soc_spi.adoc
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@ -5,7 +5,7 @@
[cols="<3,<3,<4"]
[frame="topbot",grid="none"]
|=======================
| Hardware source file(s): | neorv32_spi.vhd |
| Hardware source file(s): | neorv32_spi.vhd |
| Software driver file(s): | neorv32_spi.c |
| | neorv32_spi.h |
| Top entity port: | `spi_clk_o` | 1-bit serial clock output
@ -35,7 +35,6 @@ and not by an external SPI module. If you are looking for a _device-mode_ serial
initiated by an external host) check out the <<_serial_data_interface_controller_sdi>>.
**Theory of Operation**
The SPI module is enabled by setting the `SPI_CTRL_EN` bit in the `CTRL` control register. No transfer can be initiated

5
docs/datasheet/soc_uart.adoc
View file

@ -5,7 +5,7 @@
[cols="<3,<3,<4"]
[frame="topbot",grid="none"]
|=======================
| Hardware source file(s): | neorv32_uart.vhd |
| Hardware source file(s): | neorv32_uart.vhd |
| Software driver file(s): | neorv32_uart.c |
| | neorv32_uart.h |
| Top entity port: | `uart0_txd_o` | serial transmitter output
@ -82,6 +82,7 @@ Furthermore, a pending UART interrupt has to be explicitly cleared again by writ
Software can retrieve the configured sizes of the RX and TX FIFO via the according `UART_DATA_RX_FIFO_SIZE` and
`UART_DATA_TX_FIFO_SIZE` bits from the `DATA` register.
**RTS/CTS Hardware Flow Control**
The NEORV32 UART supports optional hardware flow control using the standard CTS `uart0_cts_i` ("clear to send") and RTS
@ -154,7 +155,7 @@ Both file are created in the simulation's home folder.
[cols="<3,<3,<4"]
[frame="topbot",grid="none"]
|=======================
| Hardware source file(s): | neorv32_uart.vhd |
| Hardware source file(s): | neorv32_uart.vhd |
| Software driver file(s): | neorv32_uart.c |
| | neorv32_uart.h |
| Top entity port: | `uart1_txd_o` | serial transmitter output