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[control] code cleanups
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stnolting
parent
baa93b641a
commit
903205649a
1 changed files with 43 additions and 53 deletions
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@ -518,10 +518,10 @@ begin
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when EX_BRANCH => -- update next PC on taken branches and jumps
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-- ------------------------------------------------------------
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exe_engine_nxt.ra <= exe_engine.pc2(XLEN-1 downto 1) & '0'; -- output return address
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ctrl_nxt.rf_wb_en <= opcode(2); -- save return address if link operation (won't happen if exception)
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exe_engine_nxt.ra <= exe_engine.pc2(XLEN-1 downto 1) & '0'; -- output return address
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ctrl_nxt.rf_wb_en <= opcode(2); -- save return address if link operation (won't happen if exception)
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trap_ctrl.instr_ma <= alu_add_i(1) and branch_taken and bool_to_ulogic_f(not RISCV_ISA_C); -- branch destination misaligned?
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if (trap_ctrl.exc_buf(exc_illegal_c) = '0') and (branch_taken = '1') then -- valid taken branch / jump
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trap_ctrl.instr_ma <= alu_add_i(1) and bool_to_ulogic_f(not RISCV_ISA_C); -- branch destination is misaligned?
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if_reset <= '1'; -- reset instruction fetch to restart at modified PC
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exe_engine_nxt.pc2 <= alu_add_i(XLEN-1 downto 1) & '0';
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exe_engine_nxt.state <= EX_BRANCHED; -- shortcut (faster than going to EX_RESTART)
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@ -839,59 +839,14 @@ begin
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-- Trap Controller
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-- ****************************************************************************************************************************
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-- Exception Buffer -----------------------------------------------------------------------
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-- Trap Buffer ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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exception_buffer: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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trap_ctrl.exc_buf <= (others => '0');
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elsif rising_edge(clk_i) then
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-- Exception Buffer -----------------------------------------------------
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-- If several exception sources trigger at once, all the requests will
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-- stay active until the trap environment is started. Only the exception
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-- with highest priority will be used to update the MCAUSE CSR. All
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-- remaining ones will be discarded.
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-- ----------------------------------------------------------------------
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-- misaligned load/store/instruction address --
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trap_ctrl.exc_buf(exc_lalign_c) <= (trap_ctrl.exc_buf(exc_lalign_c) or lsu_err_i(0)) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_salign_c) <= (trap_ctrl.exc_buf(exc_salign_c) or lsu_err_i(2)) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_ialign_c) <= (trap_ctrl.exc_buf(exc_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.env_enter);
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-- load/store/instruction access fault --
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trap_ctrl.exc_buf(exc_laccess_c) <= (trap_ctrl.exc_buf(exc_laccess_c) or lsu_err_i(1)) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_saccess_c) <= (trap_ctrl.exc_buf(exc_saccess_c) or lsu_err_i(3)) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_iaccess_c) <= (trap_ctrl.exc_buf(exc_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.env_enter);
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-- illegal instruction & environment call --
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trap_ctrl.exc_buf(exc_ecall_c) <= (trap_ctrl.exc_buf(exc_ecall_c) or trap_ctrl.ecall) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_illegal_c) <= (trap_ctrl.exc_buf(exc_illegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.env_enter);
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-- break point --
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if RISCV_ISA_Sdext then
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trap_ctrl.exc_buf(exc_ebreak_c) <= (not trap_ctrl.env_enter) and (trap_ctrl.exc_buf(exc_ebreak_c) or
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(trap_ctrl.hwtrig and (not csr.tdata1_action)) or -- trigger module fires and enter-debug-action is disabled
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(trap_ctrl.ebreak and ( csr.prv_level) and (not csr.dcsr_ebreakm) and (not debug_ctrl.run)) or -- enter M-mode handler on ebreak in M-mode
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(trap_ctrl.ebreak and (not csr.prv_level) and (not csr.dcsr_ebreaku) and (not debug_ctrl.run))); -- enter M-mode handler on ebreak in U-mode
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else
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trap_ctrl.exc_buf(exc_ebreak_c) <= (trap_ctrl.exc_buf(exc_ebreak_c) or trap_ctrl.ebreak or (trap_ctrl.hwtrig and (not csr.tdata1_action))) and (not trap_ctrl.env_enter);
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end if;
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-- debug-mode entry --
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trap_ctrl.exc_buf(exc_db_break_c) <= (trap_ctrl.exc_buf(exc_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_db_hw_c) <= (trap_ctrl.exc_buf(exc_db_hw_c) or debug_ctrl.trig_hw) and (not trap_ctrl.env_enter);
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end if;
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end process exception_buffer;
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-- Interrupt Buffer -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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interrupt_buffer: process(rstn_i, clk_i)
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trap_buffer: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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trap_ctrl.irq_pnd <= (others => '0');
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trap_ctrl.irq_buf <= (others => '0');
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trap_ctrl.exc_buf <= (others => '0');
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elsif rising_edge(clk_i) then
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-- Interrupt-Pending Buffer ---------------------------------------------
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@ -930,8 +885,43 @@ begin
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-- debug-mode entry --
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trap_ctrl.irq_buf(irq_db_halt_c) <= debug_ctrl.trig_halt or (trap_ctrl.env_pending and trap_ctrl.irq_buf(irq_db_halt_c));
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trap_ctrl.irq_buf(irq_db_step_c) <= debug_ctrl.trig_step or (trap_ctrl.env_pending and trap_ctrl.irq_buf(irq_db_step_c));
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-- Exception Buffer -----------------------------------------------------
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-- If several exception sources trigger at once, all the requests will
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-- stay active until the trap environment is started. Only the exception
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-- with highest priority will be used to update the MCAUSE CSR. All
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-- remaining ones will be discarded.
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-- ----------------------------------------------------------------------
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-- misaligned load/store/instruction address --
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trap_ctrl.exc_buf(exc_lalign_c) <= (trap_ctrl.exc_buf(exc_lalign_c) or lsu_err_i(0)) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_salign_c) <= (trap_ctrl.exc_buf(exc_salign_c) or lsu_err_i(2)) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_ialign_c) <= (trap_ctrl.exc_buf(exc_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.env_enter);
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-- load/store/instruction access fault --
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trap_ctrl.exc_buf(exc_laccess_c) <= (trap_ctrl.exc_buf(exc_laccess_c) or lsu_err_i(1)) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_saccess_c) <= (trap_ctrl.exc_buf(exc_saccess_c) or lsu_err_i(3)) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_iaccess_c) <= (trap_ctrl.exc_buf(exc_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.env_enter);
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-- illegal instruction & environment call --
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trap_ctrl.exc_buf(exc_ecall_c) <= (trap_ctrl.exc_buf(exc_ecall_c) or trap_ctrl.ecall) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_illegal_c) <= (trap_ctrl.exc_buf(exc_illegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.env_enter);
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-- break point --
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if RISCV_ISA_Sdext then
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trap_ctrl.exc_buf(exc_ebreak_c) <= (not trap_ctrl.env_enter) and (trap_ctrl.exc_buf(exc_ebreak_c) or
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(trap_ctrl.hwtrig and (not csr.tdata1_action)) or -- trigger module fires and enter-debug-action is disabled
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(trap_ctrl.ebreak and ( csr.prv_level) and (not csr.dcsr_ebreakm) and (not debug_ctrl.run)) or -- enter M-mode handler on ebreak in M-mode
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(trap_ctrl.ebreak and (not csr.prv_level) and (not csr.dcsr_ebreaku) and (not debug_ctrl.run))); -- enter M-mode handler on ebreak in U-mode
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else
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trap_ctrl.exc_buf(exc_ebreak_c) <= (trap_ctrl.exc_buf(exc_ebreak_c) or trap_ctrl.ebreak or (trap_ctrl.hwtrig and (not csr.tdata1_action))) and (not trap_ctrl.env_enter);
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end if;
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-- debug-mode entry --
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trap_ctrl.exc_buf(exc_db_break_c) <= (trap_ctrl.exc_buf(exc_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.env_enter);
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trap_ctrl.exc_buf(exc_db_hw_c) <= (trap_ctrl.exc_buf(exc_db_hw_c) or debug_ctrl.trig_hw) and (not trap_ctrl.env_enter);
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end if;
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end process interrupt_buffer;
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end process trap_buffer;
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-- Trap Priority Logic --------------------------------------------------------------------
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@ -1389,7 +1379,7 @@ begin
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csr.re <= csr.re_nxt and (not trap_ctrl.exc_buf(exc_illegal_c)); -- read if not an illegal instruction
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csr.rdata <= (others => '0'); -- default; output all-zero if there is no explicit CSR read operation
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if (csr.re = '1') then
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case csr.addr is -- address is zero if there is no CSR operation
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case csr.addr is
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-- --------------------------------------------------------------------
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-- floating-point unit
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