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⚠️ [rtl] remove core_complex rtl file
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2 changed files with 0 additions and 258 deletions
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-- ================================================================================ --
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-- NEORV32 SoC - Core Complex Top --
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-- -------------------------------------------------------------------------------- --
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-- CPU core + optional L1 I-cache + optional L1 D-cache + bus switch --
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-- -------------------------------------------------------------------------------- --
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-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
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-- Copyright (c) NEORV32 contributors. --
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-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
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-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
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-- SPDX-License-Identifier: BSD-3-Clause --
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-- ================================================================================ --
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library ieee;
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use ieee.std_logic_1164.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_core_complex is
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generic (
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-- General --
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HART_ID : natural range 0 to 3;
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NUM_HARTS : natural range 1 to 4;
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VENDOR_ID : std_ulogic_vector(31 downto 0);
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BOOT_ADDR : std_ulogic_vector(31 downto 0);
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DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0);
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DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0);
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-- RISC-V ISA Extensions --
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RISCV_ISA_C : boolean;
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RISCV_ISA_E : boolean;
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RISCV_ISA_M : boolean;
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RISCV_ISA_U : boolean;
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RISCV_ISA_Zaamo : boolean;
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RISCV_ISA_Zba : boolean;
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RISCV_ISA_Zbb : boolean;
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RISCV_ISA_Zbkb : boolean;
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RISCV_ISA_Zbkc : boolean;
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RISCV_ISA_Zbkx : boolean;
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RISCV_ISA_Zbs : boolean;
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RISCV_ISA_Zfinx : boolean;
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RISCV_ISA_Zicntr : boolean;
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RISCV_ISA_Zicond : boolean;
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RISCV_ISA_Zihpm : boolean;
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RISCV_ISA_Zknd : boolean;
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RISCV_ISA_Zkne : boolean;
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RISCV_ISA_Zknh : boolean;
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RISCV_ISA_Zksed : boolean;
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RISCV_ISA_Zksh : boolean;
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RISCV_ISA_Zmmul : boolean;
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RISCV_ISA_Zxcfu : boolean;
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RISCV_ISA_Sdext : boolean;
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RISCV_ISA_Sdtrig : boolean;
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RISCV_ISA_Smpmp : boolean;
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-- Tuning Options --
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CPU_CLOCK_GATING_EN : boolean;
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CPU_FAST_MUL_EN : boolean;
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CPU_FAST_SHIFT_EN : boolean;
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CPU_RF_HW_RST_EN : boolean;
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural range 0 to 16;
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PMP_MIN_GRANULARITY : natural;
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PMP_TOR_MODE_EN : boolean;
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PMP_NAP_MODE_EN : boolean;
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural range 0 to 13;
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HPM_CNT_WIDTH : natural range 0 to 64;
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-- Instruction Cache (iCACHE) --
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ICACHE_EN : boolean;
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ICACHE_NUM_BLOCKS : natural range 1 to 256;
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ICACHE_BLOCK_SIZE : natural range 4 to 2**16;
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ICACHE_UC_BEGIN : std_ulogic_vector(31 downto 0);
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-- Data Cache (dCACHE) --
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DCACHE_EN : boolean;
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DCACHE_NUM_BLOCKS : natural range 1 to 256;
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DCACHE_BLOCK_SIZE : natural range 4 to 2**16;
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DCACHE_UC_BEGIN : std_ulogic_vector(31 downto 0)
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);
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port (
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-- global control --
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clk_i : in std_ulogic;
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rstn_i : in std_ulogic;
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-- interrupts --
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msi_i : in std_ulogic;
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mei_i : in std_ulogic;
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mti_i : in std_ulogic;
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firq_i : in std_ulogic_vector(15 downto 0);
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dbi_i : in std_ulogic;
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-- inter-core communication links --
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icc_tx_o : out icc_t; -- TX links
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icc_rx_i : in icc_t; -- RX links
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-- system bus interface --
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bus_req_o : out bus_req_t;
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bus_rsp_i : in bus_rsp_t
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);
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end neorv32_core_complex;
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architecture neorv32_core_complex_rtl of neorv32_core_complex is
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-- bus system --
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signal cpu_i_req, cpu_d_req, icache_req, dcache_req : bus_req_t;
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signal cpu_i_rsp, cpu_d_rsp, icache_rsp, dcache_rsp : bus_rsp_t;
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begin
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-- CPU Core -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_inst: entity neorv32.neorv32_cpu
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generic map (
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-- General --
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HART_ID => HART_ID,
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NUM_HARTS => NUM_HARTS,
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VENDOR_ID => VENDOR_ID,
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BOOT_ADDR => BOOT_ADDR,
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DEBUG_PARK_ADDR => DEBUG_PARK_ADDR,
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DEBUG_EXC_ADDR => DEBUG_EXC_ADDR,
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-- RISC-V ISA Extensions --
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RISCV_ISA_C => RISCV_ISA_C,
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RISCV_ISA_E => RISCV_ISA_E,
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RISCV_ISA_M => RISCV_ISA_M,
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RISCV_ISA_U => RISCV_ISA_U,
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RISCV_ISA_Zaamo => RISCV_ISA_Zaamo,
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RISCV_ISA_Zba => RISCV_ISA_Zba,
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RISCV_ISA_Zbb => RISCV_ISA_Zbb,
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RISCV_ISA_Zbkb => RISCV_ISA_Zbkb,
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RISCV_ISA_Zbkc => RISCV_ISA_Zbkc,
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RISCV_ISA_Zbkx => RISCV_ISA_Zbkx,
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RISCV_ISA_Zbs => RISCV_ISA_Zbs,
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RISCV_ISA_Zfinx => RISCV_ISA_Zfinx,
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RISCV_ISA_Zicntr => RISCV_ISA_Zicntr,
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RISCV_ISA_Zicond => RISCV_ISA_Zicond,
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RISCV_ISA_Zihpm => RISCV_ISA_Zihpm,
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RISCV_ISA_Zknd => RISCV_ISA_Zknd,
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RISCV_ISA_Zkne => RISCV_ISA_Zkne,
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RISCV_ISA_Zknh => RISCV_ISA_Zknh,
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RISCV_ISA_Zksed => RISCV_ISA_Zksed,
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RISCV_ISA_Zksh => RISCV_ISA_Zksh,
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RISCV_ISA_Zmmul => RISCV_ISA_Zmmul,
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RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu,
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RISCV_ISA_Sdext => RISCV_ISA_Sdext,
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RISCV_ISA_Sdtrig => RISCV_ISA_Sdtrig,
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RISCV_ISA_Smpmp => RISCV_ISA_Smpmp,
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-- Tuning Options --
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CPU_CLOCK_GATING_EN => CPU_CLOCK_GATING_EN,
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CPU_FAST_MUL_EN => CPU_FAST_MUL_EN,
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CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN,
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CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN,
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS => PMP_NUM_REGIONS,
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY,
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PMP_TOR_MODE_EN => PMP_TOR_MODE_EN,
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PMP_NAP_MODE_EN => PMP_NAP_MODE_EN,
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS => HPM_NUM_CNTS,
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HPM_CNT_WIDTH => HPM_CNT_WIDTH
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)
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port map (
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-- global control --
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clk_i => clk_i,
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rstn_i => rstn_i,
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-- interrupts --
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msi_i => msi_i,
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mei_i => mei_i,
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mti_i => mti_i,
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firq_i => firq_i,
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dbi_i => dbi_i,
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-- inter-core communication links --
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icc_tx_o => icc_tx_o,
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icc_rx_i => icc_rx_i,
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-- instruction bus interface --
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ibus_req_o => cpu_i_req,
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ibus_rsp_i => cpu_i_rsp,
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-- data bus interface --
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dbus_req_o => cpu_d_req,
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dbus_rsp_i => cpu_d_rsp
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);
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-- CPU L1 Instruction Cache (I-Cache) -----------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_icache_enabled:
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if ICACHE_EN generate
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neorv32_icache_inst: entity neorv32.neorv32_cache
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generic map (
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NUM_BLOCKS => ICACHE_NUM_BLOCKS,
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BLOCK_SIZE => ICACHE_BLOCK_SIZE,
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UC_BEGIN => ICACHE_UC_BEGIN(31 downto 28),
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UC_ENABLE => true,
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READ_ONLY => true
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)
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port map (
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clk_i => clk_i,
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rstn_i => rstn_i,
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host_req_i => cpu_i_req,
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host_rsp_o => cpu_i_rsp,
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bus_req_o => icache_req,
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bus_rsp_i => icache_rsp
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);
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end generate;
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neorv32_icache_disabled:
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if not ICACHE_EN generate
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icache_req <= cpu_i_req;
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cpu_i_rsp <= icache_rsp;
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end generate;
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-- CPU L1 Data Cache (D-Cache) ------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_dcache_enabled:
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if DCACHE_EN generate
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neorv32_dcache_inst: entity neorv32.neorv32_cache
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generic map (
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NUM_BLOCKS => DCACHE_NUM_BLOCKS,
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BLOCK_SIZE => DCACHE_BLOCK_SIZE,
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UC_BEGIN => DCACHE_UC_BEGIN(31 downto 28),
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UC_ENABLE => true,
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READ_ONLY => false
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)
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port map (
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clk_i => clk_i,
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rstn_i => rstn_i,
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host_req_i => cpu_d_req,
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host_rsp_o => cpu_d_rsp,
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bus_req_o => dcache_req,
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bus_rsp_i => dcache_rsp
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);
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end generate;
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neorv32_dcache_disabled:
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if not DCACHE_EN generate
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dcache_req <= cpu_d_req;
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cpu_d_rsp <= dcache_rsp;
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end generate;
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-- Core Instruction/Data Bus Switch -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_core_bus_switch_inst: entity neorv32.neorv32_bus_switch
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generic map (
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ROUND_ROBIN_EN => false, -- use prioritizing arbitration
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PORT_A_READ_ONLY => false,
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PORT_B_READ_ONLY => true -- instruction fetch is read-only
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)
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port map (
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clk_i => clk_i,
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rstn_i => rstn_i,
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a_lock_i => '0', -- no exclusive accesses
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a_req_i => dcache_req, -- data accesses are prioritized
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a_rsp_o => dcache_rsp,
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b_req_i => icache_req,
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b_rsp_o => icache_rsp,
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x_req_o => bus_req_o,
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x_rsp_i => bus_rsp_i
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);
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end neorv32_core_complex_rtl;
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@ -19,7 +19,6 @@ NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_cpu_icc.vhd
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NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_cpu.vhd
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NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_bus.vhd
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NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_cache.vhd
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NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_core_complex.vhd
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NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_dma.vhd
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NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_application_image.vhd
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NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_imem.vhd
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