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[docs/datasheet] added sections to processor generics
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stnolting
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1 changed files with 163 additions and 17 deletions
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@ -152,6 +152,8 @@ The description of each CSR provides the following summary:
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See section <<_system_configuration_information_memory_sysinfo>> for more information.
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:sectnums!:
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===== _CLOCK_FREQUENCY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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@ -161,6 +163,9 @@ See section <<_system_configuration_information_memory_sysinfo>> for more inform
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|======
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:sectnums!:
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===== _BOOTLOADER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -171,6 +176,9 @@ processor's boot address from the beginning of the instruction memory address sp
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|======
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:sectnums!:
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===== _USER_CODE_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -179,6 +187,9 @@ processor's boot address from the beginning of the instruction memory address sp
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|======
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:sectnums!:
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===== _HW_THREAD_ID_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -187,6 +198,9 @@ processor's boot address from the beginning of the instruction memory address sp
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|======
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:sectnums!:
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===== _ON_CHIP_DEBUGGER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -202,6 +216,9 @@ processor's boot address from the beginning of the instruction memory address sp
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See section <<_instruction_sets_and_extensions>> for more information.
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_A_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -210,6 +227,9 @@ See section <<_instruction_sets_and_extensions>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -218,6 +238,9 @@ See section <<_instruction_sets_and_extensions>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_E_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -226,6 +249,9 @@ See section <<_instruction_sets_and_extensions>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_M_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -234,6 +260,9 @@ See section <<_instruction_sets_and_extensions>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_U_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -242,6 +271,9 @@ See section <<_instruction_sets_and_extensions>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -251,6 +283,9 @@ more information see section <<_zfinx_single_precision_floating_point_operations
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicsr_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -261,6 +296,9 @@ no machine information will be available.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zifencei_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -276,16 +314,23 @@ for self-modifying code (and/or for i-cache flushes).
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See section <<_instruction_sets_and_extensions>> for more information.
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:sectnums!:
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===== _FAST_MUL_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **FAST_MUL_EN** | _boolean_ | false
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3+| When this generic is enabled, the multiplier of the `M` extension is realized using DSPs blocks instead of an
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iterative bit-serial approach. This generic is only relevant when the multiplier and divider CPU extension is
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enabled (_CPU_EXTENSION_RISCV_M_ is _true_).
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enabled (<<_cpu_extension_riscv_m>> is _true_).
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|======
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:sectnums!:
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===== _FAST_SHIFT_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -295,23 +340,29 @@ more hardware resources).
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|======
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:sectnums!:
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===== _TINY_SHIFT_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **TINY_SHIFT_EN** | _boolean_ | false
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3+| If this generic is enabled the shifter unit of the CPU's ALU is implemented as (slow but tiny) single-bit iterative shifter
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(requires up to 32 clock cycles for a shift operations, but reducing hardware footprint). The configuration of
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this generic is ignored if _FAST_SHIFT_EN_ is _true_.
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this generic is ignored if <<_fast_shift_en>> is _true_.
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|======
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:sectnums!:
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===== _CPU_CNT_WIDTH_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_CNT_WIDTH** | _natural_ | 0
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3+| This generic configures the total size of the CPU's `cycle` and `instret` CSRs (low word + high word).
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The maximum value is 64, the minimal is 0. See
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section <<_machine_counters_and_timers>> for more information. Note: Configurations with _CPU_CNT_WIDTH_
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section <<_machine_counters_and_timers>> for more information. Note: Configurations with <<_cpu_cnt_width>>
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less than 64 are not RISC-V compliant.
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|======
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@ -323,16 +374,22 @@ less than 64 are not RISC-V compliant.
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See section <<_pmp_physical_memory_protection>> for more information.
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:sectnums!:
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===== _PMP_NUM_REGIONS_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **PMP_NUM_REGIONS** | _natural_ | 0
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3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
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protection logic will be implemented at all. Setting _PMP_NUM_REGIONS_ > 0 will set the _CSR_MZEXT_PMP_ flag
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in the `mzext` CSR.
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protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _CSR_MZEXT_PMP_ flag
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in the <<_mzext>> CSR.
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|======
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:sectnums!:
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===== _PMP_MIN_GRANULARITY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -347,16 +404,23 @@ in the `mzext` CSR.
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See section <<_hpm_hardware_performance_monitors>> for more information.
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:sectnums!:
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===== _HPM_NUM_CNTS_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **HPM_NUM_CNTS** | _natural_ | 0
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3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero no
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hardware performance monitor logic will be implemented at all. Setting _HPM_NUM_CNTS_ > 0 will set the _CSR_MZEXT_HPM_ flag
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in the `mzext` CSR.
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hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _CSR_MZEXT_HPM_ flag
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in the <<_mzext>> CSR.
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|======
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:sectnums!:
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===== _HPM_CNT_WIDTH_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -374,6 +438,9 @@ unused MSB-aligned counter bits are hardwired to zero.
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See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
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:sectnums!:
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===== _MEM_INT_IMEM_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -382,6 +449,9 @@ See sections <<_address_space>> and <<_instruction_memory_imem>> for more inform
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|======
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:sectnums!:
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===== _MEM_INT_IMEM_SIZE_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -390,6 +460,9 @@ See sections <<_address_space>> and <<_instruction_memory_imem>> for more inform
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|======
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:sectnums!:
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===== _MEM_INT_IMEM_ROM_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -405,6 +478,10 @@ application image at synthesis time. Has no effect when _MEM_INT_IMEM_EN_ is _fa
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See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
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:sectnums!:
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===== _MEM_INT_DMEM_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -413,6 +490,9 @@ See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
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|======
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:sectnums!:
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===== _MEM_INT_DMEM_SIZE_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -427,6 +507,10 @@ See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
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See section <<_processor_internal_instruction_cache_icache>> for more information.
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:sectnums!:
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===== _ICACHE_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -435,15 +519,21 @@ See section <<_processor_internal_instruction_cache_icache>> for more informatio
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|======
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:sectnums!:
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===== _ICACHE_NUM_BLOCK_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **ICACHE_NUM_BLOCK** | _natural_ | 4
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| **ICACHE_NUM_BLOCKS** | _natural_ | 4
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3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
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effect when _ICACHE_DMEM_EN_ is false.
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|======
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:sectnums!:
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===== _ICACHE_BLOCK_SIZE_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -453,6 +543,9 @@ _ICACHE_EN_ is _false_.
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|======
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:sectnums!:
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===== _ICACHE_ASSOCIATIVITY_
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[frame="all",grid="none"]
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|======
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@ -468,6 +561,10 @@ _ICACHE_EN_ is _false_.
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See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
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:sectnums!:
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===== _MEM_EXT_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -476,11 +573,14 @@ See sections <<_address_space>> and <<_processor_external_memory_interface_wishb
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|======
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:sectnums!:
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===== _MEM_EXT_TIMEOUT_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **MEM_EXT_TIMEOUT** | _natural_ | 255
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3+| Clock cycles after which a pending external bus access will auto-terminates and raise a bus fault exception. Set to 0 to disable auto-timeout.
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3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception. Set to 0 to disable auto-timeout.
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|======
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@ -490,6 +590,10 @@ See sections <<_address_space>> and <<_processor_external_memory_interface_wishb
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See section <<_processor_internal_modules>> for more information.
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:sectnums!:
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===== _IO_GPIO_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -499,6 +603,9 @@ See section <<_general_purpose_input_and_output_port_gpio>> for more information
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|======
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:sectnums!:
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===== _IO_MTIME_EN_
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[frame="all",grid="none"]
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|======
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@ -508,6 +615,9 @@ See section <<_machine_system_timer_mtime>> for more information.
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|======
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:sectnums!:
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===== _IO_UART0_EN_
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[frame="all",grid="none"]
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|======
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@ -518,6 +628,9 @@ more information.
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|======
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===== _IO_UART1_EN_
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[frame="all",grid="none"]
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|======
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@ -527,6 +640,9 @@ See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>>
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|======
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:sectnums!:
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===== _IO_SPI_EN_
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[frame="all",grid="none"]
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|======
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@ -536,6 +652,9 @@ See section <<_serial_peripheral_interface_controller_spi>> for more information
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|======
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:sectnums!:
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===== _IO_TWI_EN_
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[frame="all",grid="none"]
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|======
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@ -546,6 +665,9 @@ more information.
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|======
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:sectnums!:
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===== _IO_PWM_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -555,6 +677,9 @@ See section <<_pulse_width_modulation_controller_pwm>> for more information.
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|======
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:sectnums!:
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===== _IO_WDT_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -564,6 +689,9 @@ information.
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|======
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:sectnums!:
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===== _IO_TRNG_EN_
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[frame="all",grid="none"]
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|======
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@ -572,6 +700,9 @@ information.
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|======
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:sectnums!:
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===== _IO_CFS_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -580,6 +711,9 @@ information.
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|======
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:sectnums!:
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===== _IO_CFS_CONFIG_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -589,6 +723,9 @@ functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for
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|======
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:sectnums!:
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===== _IO_CFS_IN_SIZE_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -597,6 +734,9 @@ functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for
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|======
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:sectnums!:
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===== _IO_CFS_OUT_SIZE_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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@ -605,6 +745,9 @@ functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for
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|======
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:sectnums!:
|
||||
===== _IO_NCO_EN_
|
||||
|
||||
[cols="4,4,2"]
|
||||
[frame="all",grid="none"]
|
||||
|======
|
||||
|
|
@ -614,12 +757,15 @@ See section <<_numerically_controlled_oscillator_nco>> for more information.
|
|||
|======
|
||||
|
||||
|
||||
:sectnums!:
|
||||
===== _IO_NEOLED_EN_
|
||||
|
||||
[cols="4,4,2"]
|
||||
[frame="all",grid="none"]
|
||||
|======
|
||||
| **IO_NEOLED_EN** | _boolean_ | true
|
||||
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
|
||||
See section <<_smart_led_interface_neoled>> Compatible for more information.
|
||||
See section <<_smart_led_interface_neoled>> for more information.
|
||||
|======
|
||||
|
||||
|
||||
|
|
@ -772,7 +918,7 @@ denying execute right for certain region of the IMEM) can be provided using the
|
|||
[options="header",grid="rows"]
|
||||
|=======================
|
||||
| # | Region | Base address | Size | Attributes
|
||||
| 4 | IO/peripheral devices | 0xffffff00 | 256 bytes | `r/w/a/32`
|
||||
| 4 | IO/peripheral devices | 0xfffffe00 | 512 bytes | `r/w/a/32`
|
||||
| 3 | bootloader ROM | 0xffff0000 | up to 32kB| `r/x/a`
|
||||
| 2 | DMEM | 0x80000000 | up to 2GB (-64kB) | `r/w/x/a/8/16/32`
|
||||
| 1 | IMEM | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
|
||||
|
|
@ -790,11 +936,11 @@ defined by those components or the interconnection fabric.
|
|||
|
||||
The processor can implement internal memories for instructions (IMEM) and data (DMEM), which will be
|
||||
mapped to FPGA block RAMs. The implementation of these memories is controlled via the boolean
|
||||
_MEM_INT_IMEM_EN_ and _MEM_INT_DMEM_EN_ generics.
|
||||
<<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics.
|
||||
|
||||
The size of these memories are configured via the _MEM_INT_IMEM_SIZE_ and _MEM_INT_DMEM_SIZE_
|
||||
generics (in bytes), respectively. The processor-internal instruction memory (IMEM) can optionally be
|
||||
implemented as true ROM (_MEM_INT_IMEM_ROM_), which is initialized with the application code during
|
||||
implemented as true ROM (<<_mem_int_imem_rom>>), which is initialized with the application code during
|
||||
synthesis.
|
||||
|
||||
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
|
||||
|
|
@ -812,10 +958,10 @@ to the <<_processor_external_memory_interface_wishbone_axi4_lite>>:
|
|||
* access to the processor-internal DMEM and processor-internal DMEM is implemented
|
||||
* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
|
||||
|
||||
The external bus interface is available when the _MEM_EXT_EN_ generic is _true_. If this interface is
|
||||
The external bus interface is available when the <<_mem_ext_en>> generic is _true_. If this interface is
|
||||
deactivated, any access exceeding the internal memories or peripheral devices will trigger a bus access fault
|
||||
exception. If _MEM_EXT_TIMEOUT_ is greater than zero any external bus access that is not acknowledged or terminated
|
||||
within _MEM_EXT_TIMEOUT_ clock cycles will auto-timeout and raise the according bus fault exception.
|
||||
exception. If <<_mem_ext_timeout>> is greater than zero any external bus access that is not acknowledged or terminated
|
||||
within <<_mem_ext_timeout>> clock cycles will auto-timeout and raise the according bus fault exception.
|
||||
|
||||
|
||||
|
||||
|
|
@ -865,7 +1011,7 @@ from the top entity's `clk_i` signal.
|
|||
**Peripheral / IO Devices**
|
||||
|
||||
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
|
||||
address _0xFFFFF00_. A region of 256 bytes is reserved for this devices. Hence, all peripheral/IO devices are
|
||||
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
|
||||
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
|
||||
library abstract the specific memory layout for the user.
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue