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[rtl] package cleanups

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do not include packages when they are not actually used
This commit is contained in:
stnolting 2025-02-23 10:43:52 +01:00
parent 4e6d639e1d
commit 9a1d94db02
3 changed files with 7 additions and 25 deletions
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23
rtl/core/neorv32_clint.vhd
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@ -215,7 +215,7 @@ end neorv32_clint_rtl;
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
@ -224,9 +224,6 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_clint_mtime is
port (
clk_i : in std_ulogic; -- global clock line
@ -243,10 +240,9 @@ end neorv32_clint_mtime;
architecture neorv32_clint_mtime_rtl of neorv32_clint_mtime is
signal we_q, re_q : std_ulogic_vector(1 downto 0);
signal mtime_q : std_ulogic_vector(63 downto 0);
signal carry_q : std_ulogic_vector(0 downto 0);
signal inc_lo : std_ulogic_vector(32 downto 0);
signal inc_hi : std_ulogic_vector(32 downto 0);
signal mtime_q : std_ulogic_vector(63 downto 0);
signal carry_q : std_ulogic_vector(0 downto 0);
signal inc_lo, inc_hi : std_ulogic_vector(32 downto 0);
begin
@ -300,7 +296,7 @@ end neorv32_clint_mtime_rtl;
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
@ -309,9 +305,6 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_clint_mtimecmp is
port (
clk_i : in std_ulogic; -- global clock line
@ -382,13 +375,12 @@ begin
end neorv32_clint_mtimecmp_rtl;
-- ================================================================================ --
-- NEORV32 SoC - CLINT SWI (software interrupt trigger) --
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
@ -396,9 +388,6 @@ end neorv32_clint_mtimecmp_rtl;
library ieee;
use ieee.std_logic_1164.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_clint_swi is
port (
clk_i : in std_ulogic; -- global clock line

5
rtl/core/neorv32_clockgate.vhd
View file

@ -7,7 +7,7 @@
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
@ -15,9 +15,6 @@
library ieee;
use ieee.std_logic_1164.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_clockgate is
port (
clk_i : in std_ulogic; -- global clock line, always-on

4
rtl/core/neorv32_debug_auth.vhd
View file

@ -15,10 +15,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_debug_auth is
port (