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https://github.com/stnolting/neorv32.git
synced 2025-04-24 22:27:21 -04:00
[tb] add external memory init options
This commit is contained in:
stnolting
parent
ce6815ecbc
commit
9dd036f931
1 changed files with 75 additions and 44 deletions
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@ -18,8 +18,10 @@ use neorv32.neorv32_package.all;
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entity neorv32_tb is
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generic (
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-- processor --
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CLOCK_FREQUENCY : natural := 100_000_000; -- clock frequency of clk_i in Hz
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BOOT_MODE_SELECT : natural range 0 to 2 := 2; -- boot from pre-initialized IMEM
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BOOT_ADDR_CUSTOM : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CPU boot address (if boot_config = 1)
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RISCV_ISA_C : boolean := false; -- implement compressed extension
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RISCV_ISA_E : boolean := false; -- implement embedded RF extension
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RISCV_ISA_M : boolean := true; -- implement mul/div extension
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@ -54,7 +56,17 @@ entity neorv32_tb is
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ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32; -- i-cache: block size in bytes (min 4), has to be a power of 2
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DCACHE_EN : boolean := true; -- implement data cache
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DCACHE_NUM_BLOCKS : natural range 1 to 256 := 32; -- d-cache: number of blocks (min 1), has to be a power of 2
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DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32 -- d-cache: block size in bytes (min 4), has to be a power of 2
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DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32; -- d-cache: block size in bytes (min 4), has to be a power of 2
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-- external memory A --
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EXT_MEM_A_EN : boolean := true; -- enable memory
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EXT_MEM_A_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address, has to be word-aligned
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EXT_MEM_A_SIZE : natural := 64; -- memory size in bytes, min 4
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EXT_MEM_A_FILE : string := ""; -- memory initialization file (plain HEX), no initialization if empty
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-- external memory B --
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EXT_MEM_B_EN : boolean := true; -- enable memory
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EXT_MEM_B_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address, has to be word-aligned
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EXT_MEM_B_SIZE : natural := 64; -- memory size in bytes, min 4
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EXT_MEM_B_FILE : string := "" -- memory initialization file (plain HEX), no initialization if empty
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);
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end neorv32_tb;
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@ -79,8 +91,8 @@ architecture neorv32_tb_rtl of neorv32_tb is
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signal slink_tx, slink_rx : slink_t;
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-- XBUS (Wishbone b4) bus --
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signal xbus_core_req, xbus_imem_req, xbus_dmem_req, xbus_mmio_req, xbus_trig_req : xbus_req_t;
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signal xbus_core_rsp, xbus_imem_rsp, xbus_dmem_rsp, xbus_mmio_rsp, xbus_trig_rsp : xbus_rsp_t;
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signal xbus_core_req, xbus_ext_mem_a_req, xbus_ext_mem_b_req, xbus_mmio_req, xbus_trig_req : xbus_req_t;
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signal xbus_core_rsp, xbus_ext_mem_a_rsp, xbus_ext_mem_b_rsp, xbus_mmio_rsp, xbus_trig_rsp : xbus_rsp_t;
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begin
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@ -102,7 +114,7 @@ begin
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JEDEC_ID => "00000000000",
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-- Boot Configuration --
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BOOT_MODE_SELECT => BOOT_MODE_SELECT,
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BOOT_ADDR_CUSTOM => x"00000000",
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BOOT_ADDR_CUSTOM => BOOT_ADDR_CUSTOM,
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-- On-Chip Debugger (OCD) --
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OCD_EN => true,
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OCD_AUTHENTICATION => true,
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@ -142,7 +154,7 @@ begin
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HPM_NUM_CNTS => 12,
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HPM_CNT_WIDTH => 40,
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-- Internal Instruction memory --
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MEM_INT_IMEM_EN => MEM_INT_IMEM_EN ,
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MEM_INT_IMEM_EN => MEM_INT_IMEM_EN,
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MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE,
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-- Internal Data memory --
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MEM_INT_DMEM_EN => MEM_INT_DMEM_EN,
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@ -352,9 +364,9 @@ begin
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-- -------------------------------------------------------------------------------------------
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sim_rx_uart0: entity work.sim_uart_rx
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generic map (
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name => "uart0",
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fclk => real(CLOCK_FREQUENCY),
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baud => real(19200)
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NAME => "uart0",
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FCLK => real(CLOCK_FREQUENCY),
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BAUD => real(19200)
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)
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port map (
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clk => clk_gen,
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@ -363,9 +375,9 @@ begin
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sim_rx_uart1: entity work.sim_uart_rx
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generic map (
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name => "uart1",
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fclk => real(CLOCK_FREQUENCY),
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baud => real(19200)
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NAME => "uart1",
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FCLK => real(CLOCK_FREQUENCY),
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BAUD => real(19200)
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)
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port map (
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clk => clk_gen,
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@ -378,51 +390,69 @@ begin
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xbus_interconnect: entity work.xbus_gateway
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generic map (
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-- device address size in bytes and base address --
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DEV_0_SIZE => MEM_INT_IMEM_SIZE, DEV_0_BASE => mem_imem_base_c,
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DEV_1_SIZE => MEM_INT_DMEM_SIZE, DEV_1_BASE => mem_dmem_base_c,
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DEV_2_SIZE => 64, DEV_2_BASE => x"F0000000",
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DEV_3_SIZE => 4, DEV_3_BASE => x"FF000000"
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DEV_0_EN => EXT_MEM_A_EN, DEV_0_SIZE => EXT_MEM_A_SIZE, DEV_0_BASE => EXT_MEM_A_BASE,
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DEV_1_EN => EXT_MEM_B_EN, DEV_1_SIZE => EXT_MEM_B_SIZE, DEV_1_BASE => EXT_MEM_B_BASE,
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DEV_2_EN => true, DEV_2_SIZE => 64, DEV_2_BASE => x"F0000000",
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DEV_3_EN => true, DEV_3_SIZE => 4, DEV_3_BASE => x"FF000000"
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)
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port map (
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-- host port --
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host_req_i => xbus_core_req,
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host_rsp_o => xbus_core_rsp,
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-- device ports --
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dev_0_req_o => xbus_imem_req, dev_0_rsp_i => xbus_imem_rsp,
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dev_1_req_o => xbus_dmem_req, dev_1_rsp_i => xbus_dmem_rsp,
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dev_2_req_o => xbus_mmio_req, dev_2_rsp_i => xbus_mmio_rsp,
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dev_3_req_o => xbus_trig_req, dev_3_rsp_i => xbus_trig_rsp
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dev_0_req_o => xbus_ext_mem_a_req, dev_0_rsp_i => xbus_ext_mem_a_rsp,
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dev_1_req_o => xbus_ext_mem_b_req, dev_1_rsp_i => xbus_ext_mem_b_rsp,
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dev_2_req_o => xbus_mmio_req, dev_2_rsp_i => xbus_mmio_rsp,
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dev_3_req_o => xbus_trig_req, dev_3_rsp_i => xbus_trig_rsp
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);
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-- XBUS: Instruction Memory ---------------------------------------------------------------
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-- XBUS: External Memory A ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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xbus_imem: entity work.xbus_memory
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generic map (
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MEM_SIZE => MEM_INT_IMEM_SIZE,
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MEM_LATE => 1
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)
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port map (
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clk_i => clk_gen,
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rstn_i => rst_gen,
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xbus_req_i => xbus_imem_req,
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xbus_rsp_o => xbus_imem_rsp
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);
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xbus_external_memory_a_enable:
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if EXT_MEM_A_EN generate
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xbus_external_memory_a: entity work.xbus_memory
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generic map (
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MEM_SIZE => EXT_MEM_A_SIZE,
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MEM_LATE => 1,
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MEM_FILE => EXT_MEM_A_FILE
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)
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port map (
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clk_i => clk_gen,
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rstn_i => rst_gen,
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xbus_req_i => xbus_ext_mem_a_req,
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xbus_rsp_o => xbus_ext_mem_a_rsp
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);
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end generate;
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xbus_external_memory_a_disable:
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if not EXT_MEM_A_EN generate
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xbus_ext_mem_a_rsp <= xbus_rsp_terminate_c;
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end generate;
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-- XBUS: Data Memory ----------------------------------------------------------------------
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-- XBUS: External Memory B ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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xbus_dmem: entity work.xbus_memory
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generic map (
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MEM_SIZE => MEM_INT_DMEM_SIZE,
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MEM_LATE => 1
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)
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port map (
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clk_i => clk_gen,
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rstn_i => rst_gen,
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xbus_req_i => xbus_dmem_req,
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xbus_rsp_o => xbus_dmem_rsp
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);
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xbus_external_memory_b_enable:
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if EXT_MEM_B_EN generate
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xbus_external_memory_b: entity work.xbus_memory
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generic map (
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MEM_SIZE => EXT_MEM_B_SIZE,
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MEM_LATE => 1,
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MEM_FILE => EXT_MEM_B_FILE
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)
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port map (
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clk_i => clk_gen,
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rstn_i => rst_gen,
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xbus_req_i => xbus_ext_mem_b_req,
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xbus_rsp_o => xbus_ext_mem_b_rsp
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);
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end generate;
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xbus_external_memory_b_disable:
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if not EXT_MEM_B_EN generate
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xbus_ext_mem_b_rsp <= xbus_rsp_terminate_c;
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end generate;
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-- XBUS: Memory-Mapped IO -----------------------------------------------------------------
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@ -430,7 +460,8 @@ begin
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xbus_mmio: entity work.xbus_memory
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generic map (
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MEM_SIZE => 64,
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MEM_LATE => 32
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MEM_LATE => 32,
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MEM_FILE => "" -- no initialization
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)
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port map (
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clk_i => clk_gen,
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