github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 14:17:51 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

✨ add support for RISC-V Zbkc ISA extension (#1038)

Browse source
This commit is contained in:
stnolting 2024-09-27 22:38:07 +02:00 • committed by GitHub
commit a30c03045e
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
20 changed files with 173 additions and 71 deletions
Download patch file Download diff file Expand all files Collapse all files

1
CHANGELOG.md
View file

@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 27.09.2024 | 1.10.4.7 | :sparkles: add support for RISC-V "carry-less multiplication instruction for cryptography" ISA extension `Zbkc` | [#1038](https://github.com/stnolting/neorv32/pull/1038) |
| 27.09.2024 | 1.10.4.6 | :sparkles: add support for RISC-V "bit manipulation instructions for cryptography" ISA extension `Zbkb` | [#1037](https://github.com/stnolting/neorv32/pull/1037) |
| 27.09.2024 | 1.10.4.5 | :sparkles: add support for RISC-V "data independent execution time" ISA extension `Zknt` | [#1036](https://github.com/stnolting/neorv32/pull/1036) |
| 25.09.2024 | 1.10.4.4 | :sparkles: add support for RISC-V "scalar cryptography" ISA extensions `Zbkx`, `Zknd`, `Zkne`, `Zknh` | [#1033](https://github.com/stnolting/neorv32/pull/1033) |

2
README.md
View file

@ -62,6 +62,7 @@ not working as expected. See how to [contribute](https://github.com/stnolting/ne
- [x] FPGA friendly (e.g. _all_ internal memories can be mapped to block RAM - including the CPU's register file)
- [x] optimized for high clock frequencies to ease integration / timing closure
- [x] from zero to _"hello world!"_ - completely open source and documented
- [x] highly documented - on software and hardware side
- [x] easy to use even for FPGA / RISC-V starters – intended to work _out of the box_
### Project Status
@ -109,6 +110,7 @@ setup according to your needs. Note that all of the following SoC modules are en
[[`U`](https://stnolting.github.io/neorv32/#_u_isa_extension)]
[[`X`](https://stnolting.github.io/neorv32/#_x_isa_extension)]
[[`Zbkb`](https://stnolting.github.io/neorv32/#_zbkb_isa_extension)]
[[`Zbkc`](https://stnolting.github.io/neorv32/#_zbkc_isa_extension)]
[[`Zbkx`](https://stnolting.github.io/neorv32/#_zbkx_isa_extension)]
[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_isa_extension)]
[[`Zicond`](https://stnolting.github.io/neorv32/#_zicond_isa_extension)]

22
docs/datasheet/cpu.adoc
View file

@ -441,6 +441,7 @@ This chapter gives a brief overview of all available ISA extensions.
| <<_u_isa_extension,`U`>> | Less-privileged _user_ mode extension | `CPU_EXTENSION_RISCV_U`
| <<_x_isa_extension,`X`>> | Platform-specific / NEORV32-specific extension | Always enabled
| <<_zbkb_isa_extension,`Zbkb`>> | Scalar cryptographic bit manipulation instructions | `CPU_EXTENSION_RISCV_Zbkb`
| <<_zbkc_isa_extension,`Zbkc`>> | Scalar cryptographic carry-less multiplication instructions | `CPU_EXTENSION_RISCV_Zbkc`
| <<_zbkx_isa_extension,`Zbkx`>> | Scalar cryptographic crossbar permutation instructions | `CPU_EXTENSION_RISCV_Zbkx`
| <<_zfinx_isa_extension,`Zfinx`>> | Floating-point instructions using integer registers | `CPU_EXTENSION_RISCV_Zfinx`
| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction | Always enabled
@ -544,9 +545,9 @@ The NEORV32 `B` ISA extension includes the following sub-extensions:
|=======================
| Class | Instructions | Execution cycles
| Arithmetic/logic | `min[u]` `max[u]` `sext.b` `sext.h` `andn` `orn` `xnor` `zext`(pack) `rev8` `orc.b` | 4
| Shifts | `clz` `ctz` | 3 + 1..32; FAST_SHIFT: 4
| Shifts | `cpop` | 36; FAST_SHIFT: 4
| Shifts | `rol` `ror[i]` | 4 + _shift_amount_; FAST_SHIFT: 4
| Shifts | `clz` `ctz` | 6 + 1..32; FAST_SHIFT: 4
| Shifts | `cpop` | 6 + 32; FAST_SHIFT: 4
| Shifts | `rol` `ror[i]` | 6 + _shift_amount_; FAST_SHIFT: 4
| Shifted-add | `sh1add` `sh2add` `sh3add` | 4
| Single-bit | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 4
|=======================
@ -815,6 +816,21 @@ This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neo
|=======================
==== `Zbkc` ISA Extension
The `Zbkc` sub-extension is part of the _RISC-V scalar cryptography_ ISA extension and adds carry-less multiplication instruction.
ISA extension with additional instructions. It is enabled by the top's `CPU_EXTENSION_RISCV_Zbkc` generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_bitmanip.vhd`).
.Instructions and Timing
[cols="<2,<4,<3"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Carry-less multiply | `clmul` `clmulh` | 6 + 32
|=======================
==== `Zbkx` ISA Extension
The `Zbkx` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds crossbar permutation instructions.

3
docs/datasheet/cpu_csr.adoc
View file

@ -964,7 +964,8 @@ discover ISA sub-extensions and CPU configuration options
| 14 | `CSR_MXISA_ZKNE` | r/- | <<_zkne_isa_extension>> available
| 15 | `CSR_MXISA_ZKNH` | r/- | <<_zknh_isa_extension>> available
| 16 | `CSR_MXISA_ZBKB` | r/- | <<_zbkb_isa_extension>> available
| 19:17 | - | r/- | hardwired to zero
| 17 | `CSR_MXISA_ZBKC` | r/- | <<_zbkc_isa_extension>> available
| 19:18 | - | r/- | hardwired to zero
| 20 | `CSR_MXISA_IS_SIM` | r/- | set if CPU is being **simulated** (⚠️ not guaranteed)
| 28:21 | - | r/- | hardwired to zero
| 29 | `CSR_MXISA_RFHWRST` | r/- | full hardware reset of register file available when set (`REGFILE_HW_RST`)

4
docs/datasheet/on_chip_debugger.adoc
View file

@ -540,7 +540,7 @@ asynchronous interrupts) that are handled transparently by the control logic.
* switch to debug-mode privilege level
* move the current program counter to <<_dpc>>
* copy the hart's current privilege level to the `prv` flags in <<_dcsr>>
* set `cause` in <<_dcrs>> according to the cause why debug mode is entered
* set `cause` in <<_dcsr>> according to the cause why debug mode is entered
* **no update** of `mtval`, `mcause`, `mtval` and `mstatus` CSRs
* load the address configured via the CPU's `CPU_DEBUG_PARK_ADDR` (<<_cpu_top_entity_generics>>) generic to the program counter jumping to the
"debugger park loop" code stored in the debug module (DM)
@ -564,7 +564,7 @@ Executing `dret` outside of debug mode will raise an illegal instruction excepti
**Whenever the CPU leaves debug mode it performs the following operations:**
* set the hart's current privilege level according to the `prv` flags of <<_dcsr>>
* restore the original program counter from <<_dpcs>> resuming normal operation
* restore the original program counter from <<_dpc>> resuming normal operation
:sectnums:

11
docs/datasheet/soc.adoc
View file

@ -211,16 +211,17 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
| `CPU_EXTENSION_RISCV_E` | boolean | false | Enable <<_e_isa_extension>> (reduced register file size).
| `CPU_EXTENSION_RISCV_M` | boolean | false | Enable <<_m_isa_extension>> (hardware-based integer multiplication and division).
| `CPU_EXTENSION_RISCV_U` | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode).
| `CPU_EXTENSION_RISCV_Zbkb` | boolean | false | Enable <<_zbkb_isa_extension>> (scalar cryptography bit manipulation operations).
| `CPU_EXTENSION_RISCV_Zbkb` | boolean | false | Enable <<_zbkb_isa_extension>> (scalar cryptography bit manipulation instructions).
| `CPU_EXTENSION_RISCV_Zbkc` | boolean | false | Enable <<_zbkc_isa_extension>> (scalar cryptography carry-less multiplication instructions).
| `CPU_EXTENSION_RISCV_Zbkx` | boolean | false | Enable <<_zbkx_isa_extension>> (scalar cryptography crossbar permutations).
| `CPU_EXTENSION_RISCV_Zfinx` | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit).
| `CPU_EXTENSION_RISCV_Zicntr` | boolean | true | Enable <<_zicntr_isa_extension>> (CPU base counters).
| `CPU_EXTENSION_RISCV_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional operations).
| `CPU_EXTENSION_RISCV_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional instructions).
| `CPU_EXTENSION_RISCV_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors).
| `CPU_EXTENSION_RISCV_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
| CPU_EXTENSION_RISCV_Zknd` | boolean | false | Enable <<_Zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
| CPU_EXTENSION_RISCV_Zkne` | boolean | false | Enable <<_Zkne_isa_extension>> (scalar cryptography NIST AES encryption instructions).
| CPU_EXTENSION_RISCV_Zknh` | boolean | false | Enable <<_Zknh_isa_extension>> (scalar cryptography NIST hash instructions).
| CPU_EXTENSION_RISCV_Zknd` | boolean | false | Enable <<_zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
| CPU_EXTENSION_RISCV_Zkne` | boolean | false | Enable <<_zkne_isa_extension>> (scalar cryptography NIST AES encryption instructions).
| CPU_EXTENSION_RISCV_Zknh` | boolean | false | Enable <<_zknh_isa_extension>> (scalar cryptography NIST hash instructions).
| `CPU_EXTENSION_RISCV_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).
4+^| **CPU <<_architecture>> Tuning Options**
| `FAST_MUL_EN` | boolean | false | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.

BIN
docs/figures/neorv32_processor.png
View file

Binary file not shown.
Side by side Swipe Overlay

Before

Width:  |  Height:  |  Size: 138 KiB

After

Width:  |  Height:  |  Size: 139 KiB

Before After
Before After

14
rtl/core/neorv32_cpu.vhd
View file

@ -35,6 +35,7 @@ entity neorv32_cpu is
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkc : boolean; -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx : boolean; -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
@ -86,8 +87,8 @@ end neorv32_cpu;
architecture neorv32_cpu_rtl of neorv32_cpu is
-- auto-configuration --
constant regfile_rs3_en_c : boolean := CPU_EXTENSION_RISCV_Zxcfu or CPU_EXTENSION_RISCV_Zfinx; -- 3rd register file read port
constant fixed_latency_en_c : boolean := FAST_SHIFT_EN; -- data-independent execution time for crypto operations (RISC-V Zknt ISA ext.)
constant rf_rs3_en_c : boolean := CPU_EXTENSION_RISCV_Zxcfu or CPU_EXTENSION_RISCV_Zfinx; -- 3rd register file read port
constant const_exe_c : boolean := FAST_SHIFT_EN; -- data-independent execution time for crypto operations (RISC-V Zknt ISA ext.)
-- external CSR interface --
signal xcsr_we : std_ulogic;
@ -132,6 +133,7 @@ begin
cond_sel_string_f(CPU_EXTENSION_RISCV_U, "u", "" ) &
cond_sel_string_f(true, "x", "" ) & -- always enabled
cond_sel_string_f(CPU_EXTENSION_RISCV_Zbkb, "_zbkb", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zbkc, "_zbkc", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zbkx, "_zbkx", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_zicntr", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicond, "_zicond", "" ) &
@ -142,7 +144,7 @@ begin
cond_sel_string_f(CPU_EXTENSION_RISCV_Zknd, "_zknd", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zkne, "_zkne", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zknh, "_zknh", "" ) &
cond_sel_string_f(fixed_latency_en_c, "_zknt", "" ) &
cond_sel_string_f(const_exe_c, "_zknt", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_zmmul", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_zxcfu", "" ) &
cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext, "_sdext", "" ) &
@ -179,6 +181,7 @@ begin
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkb => CPU_EXTENSION_RISCV_Zbkb, -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkc => CPU_EXTENSION_RISCV_Zbkc, -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx => CPU_EXTENSION_RISCV_Zbkx, -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
@ -187,7 +190,7 @@ begin
CPU_EXTENSION_RISCV_Zknd => CPU_EXTENSION_RISCV_Zknd, -- implement cryptography NIST AES decryption extension?
CPU_EXTENSION_RISCV_Zkne => CPU_EXTENSION_RISCV_Zkne, -- implement cryptography NIST AES encryption extension?
CPU_EXTENSION_RISCV_Zknh => CPU_EXTENSION_RISCV_Zknh, -- implement cryptography NIST hash extension?
CPU_EXTENSION_RISCV_Zknt => fixed_latency_en_c, -- data-independent execution time available (for cryptographic operations)?
CPU_EXTENSION_RISCV_Zknt => const_exe_c, -- data-independent execution time available (for cryptographic operations)?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_Sdext => CPU_EXTENSION_RISCV_Sdext, -- implement external debug mode extension?
@ -253,7 +256,7 @@ begin
generic map (
RST_EN => REGFILE_HW_RST, -- enable dedicated hardware reset ("ASIC style")
RVE_EN => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension
RS3_EN => regfile_rs3_en_c -- enable 3rd read port
RS3_EN => rf_rs3_en_c -- enable 3rd read port
)
port map (
-- global control --
@ -280,6 +283,7 @@ begin
CPU_EXTENSION_RISCV_Zba => CPU_EXTENSION_RISCV_B, -- implement address-generation instruction
CPU_EXTENSION_RISCV_Zbb => CPU_EXTENSION_RISCV_B, -- implement basic bit-manipulation instruction
CPU_EXTENSION_RISCV_Zbkb => CPU_EXTENSION_RISCV_Zbkb, -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkc => CPU_EXTENSION_RISCV_Zbkc, -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx => CPU_EXTENSION_RISCV_Zbkx, -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zbs => CPU_EXTENSION_RISCV_B, -- implement single-bit instructions
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)

20
rtl/core/neorv32_cpu_alu.vhd
View file

@ -19,12 +19,13 @@ entity neorv32_cpu_alu is
generic (
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
CPU_EXTENSION_RISCV_Zba : boolean; -- implement address-generation instruction
CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation instruction
CPU_EXTENSION_RISCV_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zba : boolean; -- implement address-generation instruction?
CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation instruction?
CPU_EXTENSION_RISCV_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography?
CPU_EXTENSION_RISCV_Zbkc : boolean; -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx : boolean; -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zbs : boolean; -- implement single-bit instructions
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zbs : boolean; -- implement single-bit instructions?
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)?
CPU_EXTENSION_RISCV_Zicond : boolean; -- implement integer conditional operations?
CPU_EXTENSION_RISCV_Zknd : boolean; -- implement cryptography NIST AES decryption extension?
CPU_EXTENSION_RISCV_Zkne : boolean; -- implement cryptography NIST AES encryption extension?
@ -216,13 +217,15 @@ begin
-- ALU[I]-Opcode Co-Processor: Bit-Manipulation Unit ('B' ISA Extension) ------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_cp_bitmanip_inst_true:
if CPU_EXTENSION_RISCV_Zba or CPU_EXTENSION_RISCV_Zbb or CPU_EXTENSION_RISCV_Zbkb or CPU_EXTENSION_RISCV_Zbs generate
if CPU_EXTENSION_RISCV_Zba or CPU_EXTENSION_RISCV_Zbb or CPU_EXTENSION_RISCV_Zbkb or
CPU_EXTENSION_RISCV_Zbs or CPU_EXTENSION_RISCV_Zbkc generate
neorv32_cpu_cp_bitmanip_inst: entity neorv32.neorv32_cpu_cp_bitmanip
generic map (
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
EN_FAST_SHIFT => FAST_SHIFT_EN, -- use barrel shifter for shift operations
EN_ZBA => CPU_EXTENSION_RISCV_Zba, -- enable address-generation instruction
EN_ZBB => CPU_EXTENSION_RISCV_Zbb, -- enable basic bit-manipulation instruction
EN_ZBKB => CPU_EXTENSION_RISCV_Zbkb, -- enable bit-manipulation instructions for cryptography
EN_ZBKC => CPU_EXTENSION_RISCV_Zbkc, -- enable carry-less multiplication instructions
EN_ZBS => CPU_EXTENSION_RISCV_Zbs -- enable single-bit instructions
)
port map (
@ -242,7 +245,8 @@ begin
end generate;
neorv32_cpu_cp_bitmanip_inst_false:
if not (CPU_EXTENSION_RISCV_Zba or CPU_EXTENSION_RISCV_Zbb or CPU_EXTENSION_RISCV_Zbkb or CPU_EXTENSION_RISCV_Zbs) generate
if not (CPU_EXTENSION_RISCV_Zba or CPU_EXTENSION_RISCV_Zbb or CPU_EXTENSION_RISCV_Zbkb or
CPU_EXTENSION_RISCV_Zbs or CPU_EXTENSION_RISCV_Zbkc) generate
cp_result(2) <= (others => '0');
cp_valid(2) <= '0';
end generate;

4
rtl/core/neorv32_cpu_control.vhd
View file

@ -41,7 +41,8 @@ entity neorv32_cpu_control is
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded-class register file extension?
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography?
CPU_EXTENSION_RISCV_Zbkc : boolean; -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx : boolean; -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT regs)?
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
@ -1896,6 +1897,7 @@ begin
csr.rdata(14) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zkne); -- Zkne: cryptography NIST AES encryption
csr.rdata(15) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zknh); -- Zknh: cryptography NIST hash functions
csr.rdata(16) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zbkb); -- Zbkb: bit manipulation instructions for cryptography
csr.rdata(17) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zbkc); -- Zbkc: carry-less multiplication for cryptography
-- misc --
csr.rdata(20) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
-- tuning options --

121
rtl/core/neorv32_cpu_cp_bitmanip.vhd
View file

@ -6,6 +6,7 @@
-- + Zbb: Basic bit-manipulation instructions --
-- + Zbs: Single-bit instructions --
-- + Zbkb: Bit-manipulation instructions for cryptography --
-- + Zbkc: Carry-less multiplication instructions for cryptography --
-- [NOTE] RISC-V "B" ISA Extension = Zba + Zbb + Zbs --
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
@ -24,9 +25,10 @@ use neorv32.neorv32_package.all;
entity neorv32_cpu_cp_bitmanip is
generic (
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
EN_ZBA : boolean; -- enable address-generation instruction
EN_ZBB : boolean; -- enable basic bit-manipulation instruction
EN_FAST_SHIFT : boolean; -- use barrel shifter for shift operations
EN_ZBA : boolean; -- enable address-generation instructions
EN_ZBB : boolean; -- enable basic bit-manipulation instructions
EN_ZBKC : boolean; -- enable carry-less multiplication instructions
EN_ZBKB : boolean; -- enable bit-manipulation instructions for cryptography
EN_ZBS : boolean -- enable single-bit instructions
);
@ -71,11 +73,13 @@ architecture neorv32_cpu_cp_bitmanip_rtl of neorv32_cpu_cp_bitmanip is
constant op_pack_c : natural := 16; -- pack bytes/halves
constant op_zip_c : natural := 17; -- (de)interleave
constant op_brev8_c : natural := 18; -- byte-wise bit-reverse
-- Zbkc --
constant op_clmul_c : natural := 19; -- carry-less multiplication
--
constant op_width_c : natural := 19;
constant op_width_c : natural := 20;
-- controller --
type ctrl_state_t is (S_IDLE, S_START_SHIFT, S_BUSY_SHIFT);
type ctrl_state_t is (S_IDLE, S_START, S_BUSY);
signal ctrl_state : ctrl_state_t;
signal valid_cmd : std_ulogic;
signal cmd : std_ulogic_vector(op_width_c-1 downto 0);
@ -99,6 +103,15 @@ architecture neorv32_cpu_cp_bitmanip_rtl of neorv32_cpu_cp_bitmanip is
end record;
signal shifter : shifter_t;
-- serial carry-less multiplier --
type clmul_t is record
start : std_ulogic;
run : std_ulogic;
cnt : std_ulogic_vector(index_size_f(XLEN) downto 0);
res : std_ulogic_vector(2*XLEN-1 downto 0);
end record;
signal clmul : clmul_t;
-- barrel shifter --
type bs_level_t is array (index_size_f(XLEN) downto 0) of std_ulogic_vector(XLEN-1 downto 0);
signal bs_level : bs_level_t;
@ -144,13 +157,16 @@ begin
cmd(op_zip_c) <= '1' when EN_ZBKB and (ctrl_i.ir_opcode(5) = '0') and (ctrl_i.ir_funct12 = "000010001111") and ((ctrl_i.ir_funct3 = "001") or (ctrl_i.ir_funct3 = "101")) else '0'; -- [UN]ZIP
cmd(op_brev8_c) <= '1' when EN_ZBKB and (ctrl_i.ir_opcode(5) = '0') and (ctrl_i.ir_funct12 = "011010000111") and (ctrl_i.ir_funct3 = "101") else '0'; -- BREV8
-- Zbkc - Carry-less multiplication instructions --
cmd(op_clmul_c) <= '1' when EN_ZBKC and (ctrl_i.ir_opcode(5) = '1') and (ctrl_i.ir_funct12(11 downto 5) = "0000101") and (ctrl_i.ir_funct3(2) = '0') and (ctrl_i.ir_funct3(0) = '1') else '0'; -- CLMUL[H]
-- Valid Instruction? --
valid_cmd <= '1' when (ctrl_i.alu_cp_alu = '1') and (or_reduce_f(cmd) = '1') else '0';
-- Co-Processor Controller ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
coprocessor_ctrl: process(rstn_i, clk_i)
controller: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl_state <= S_IDLE;
@ -159,13 +175,15 @@ begin
sha_reg <= (others => '0');
less_reg <= '0';
shifter.start <= '0';
clmul.start <= '0';
valid <= '0';
elsif rising_edge(clk_i) then
-- defaults --
shifter.start <= '0';
clmul.start <= '0';
valid <= '0';
-- operand registers --
-- operand gating / buffering --
if (ctrl_i.alu_cp_alu = '1') then
less_reg <= cmp_i(cmp_less_c);
rs1_reg <= rs1_i;
@ -179,39 +197,38 @@ begin
when S_IDLE => -- wait for operation trigger
-- ------------------------------------------------------------
if (valid_cmd = '1') then
if (not FAST_SHIFT_EN) and ((cmd(op_cz_c) or cmd(op_cpop_c) or cmd(op_rot_c)) = '1') then -- multi-cycle shift operation
if (not EN_FAST_SHIFT) and ((cmd(op_cz_c) or cmd(op_cpop_c) or cmd(op_rot_c)) = '1') then -- multi-cycle shift operation
shifter.start <= '1';
ctrl_state <= S_START_SHIFT;
ctrl_state <= S_START;
elsif (cmd(op_clmul_c) = '1') then -- multi-cycle carry-less multiplication operation
clmul.start <= '1';
ctrl_state <= S_START;
else
valid <= '1';
ctrl_state <= S_IDLE;
end if;
end if;
when S_START_SHIFT => -- one cycle delay to start shift operation
when S_START => -- one cycle delay to start iterative operation
-- ------------------------------------------------------------
ctrl_state <= S_BUSY_SHIFT;
ctrl_state <= S_BUSY;
when S_BUSY_SHIFT => -- wait for multi-cycle shift operation to finish
when others => -- S_BUSY: wait for multi-cycle operation to finish
-- ------------------------------------------------------------
if (shifter.run = '0') or (ctrl_i.cpu_trap = '1') then -- abort on trap
if ((shifter.run = '0') and (clmul.run = '0')) or (ctrl_i.cpu_trap = '1') then -- abort on trap
valid <= '1';
ctrl_state <= S_IDLE;
end if;
when others => -- undefined
-- ------------------------------------------------------------
ctrl_state <= S_IDLE;
end case;
end if;
end process coprocessor_ctrl;
end process controller;
-- Shifter Function Core (iterative: small but slow) --------------------------------------
-- -------------------------------------------------------------------------------------------
serial_shifter:
if not FAST_SHIFT_EN generate
if not EN_FAST_SHIFT generate
serial_shifter_core: process(rstn_i, clk_i)
begin
@ -225,8 +242,7 @@ begin
shifter.cnt <= (others => '0');
shifter.sreg <= rs1_reg;
if (cmd(op_cpop_c) = '1') then -- population count
shifter.cnt_max <= (others => '0');
shifter.cnt_max(shifter.cnt_max'left) <= '1';
shifter.cnt_max <= std_ulogic_vector(to_unsigned(XLEN, shifter.cnt_max'length));
else
shifter.cnt_max <= '0' & shamt_i;
end if;
@ -276,7 +292,7 @@ begin
-- Shifter Function Core (parallel: fast but large) ---------------------------------------
-- -------------------------------------------------------------------------------------------
barrel_shifter:
if FAST_SHIFT_EN generate
if EN_FAST_SHIFT generate
-- rotator input layer: convert left-rotates to right-rotates (rotate by XLEN - N positions) --
bs_shift <= std_ulogic_vector(unsigned(not sha_reg) + 1) when (ctrl_i.ir_funct3(2) = '0') else sha_reg;
@ -328,6 +344,45 @@ begin
end process shift_one_hot;
-- Carry-Less Multiplier ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
clmul_enable:
if EN_ZBKC generate
clmul_core: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
clmul.cnt <= (others => '0');
clmul.res <= (others => '0');
elsif rising_edge(clk_i) then
if (clmul.start = '1') then -- start new multiplication
clmul.cnt <= std_ulogic_vector(to_unsigned(XLEN, clmul.cnt'length));
clmul.res <= replicate_f('0', XLEN) & rs1_reg;
elsif (clmul.run = '1') then -- operation in progress
clmul.cnt <= std_ulogic_vector(unsigned(clmul.cnt) - 1);
if (clmul.res(0) = '1') then
clmul.res(2*XLEN-2 downto XLEN-1) <= clmul.res(2*XLEN-1 downto XLEN) xor rs2_reg;
else
clmul.res(2*XLEN-2 downto XLEN-1) <= clmul.res(2*XLEN-1 downto XLEN);
end if;
clmul.res(XLEN-2 downto 0) <= clmul.res(XLEN-1 downto 1);
end if;
end if;
end process clmul_core;
-- operation in progress --
clmul.run <= '1' when (or_reduce_f(clmul.cnt) = '1') else '0';
end generate;
clmul_disable:
if not EN_ZBKC generate
clmul.cnt <= (others => '0');
clmul.res <= (others => '0');
clmul.run <= '1';
end generate;
-- Operation Results ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- logic with negate --
@ -352,8 +407,8 @@ begin
res_int(op_sext_c)(7 downto 0) <= rs1_reg(7 downto 0);
-- zero-extension --
res_int(op_zexth_c)(XLEN-1 downto 16) <= (others => '0');
res_int(op_zexth_c)(15 downto 0) <= rs1_reg(15 downto 0);
res_int(op_zexth_c)(XLEN-1 downto XLEN/2) <= (others => '0');
res_int(op_zexth_c)(XLEN/2-1 downto 0) <= rs1_reg(XLEN/2-1 downto 0);
-- rotate right/left --
res_int(op_rot_c) <= shifter.sreg;
@ -378,8 +433,8 @@ begin
res_int(op_bset_c) <= rs1_reg or one_hot_res;
-- pack --
res_int(op_pack_c) <= rs2_reg(15 downto 0) & rs1_reg(15 downto 0) when (ctrl_i.ir_funct3(0) = '0') else
x"0000" & rs2_reg(7 downto 0) & rs1_reg(7 downto 0);
res_int(op_pack_c) <= rs2_reg(XLEN/2-1 downto 0) & rs1_reg(XLEN/2-1 downto 0) when (ctrl_i.ir_funct3(0) = '0') else
replicate_f('0', XLEN/2) & rs2_reg(7 downto 0) & rs1_reg(7 downto 0);
-- zip/unzip --
interleave_gen:
@ -397,6 +452,9 @@ begin
res_int(op_brev8_c)(i*8+7 downto i*8) <= bit_rev_f(rs1_reg(i*8+7 downto i*8));
end generate;
-- carry-less multiplication --
res_int(op_clmul_c) <= clmul.res(2*XLEN-1 downto XLEN) when (ctrl_i.ir_funct3(1) = '1') else clmul.res(XLEN-1 downto 0);
-- Output Select --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
@ -419,6 +477,7 @@ begin
res_out(op_pack_c) <= res_int(op_pack_c) when EN_ZBKB and (cmd(op_pack_c) = '1') else (others => '0');
res_out(op_zip_c) <= res_int(op_zip_c) when EN_ZBKB and (cmd(op_zip_c) = '1') else (others => '0');
res_out(op_brev8_c) <= res_int(op_brev8_c) when EN_ZBKB and (cmd(op_brev8_c) = '1') else (others => '0');
res_out(op_clmul_c) <= res_int(op_clmul_c) when EN_ZBKC and (cmd(op_clmul_c) = '1') else (others => '0');
-- Output Gate ----------------------------------------------------------------------------
@ -430,11 +489,11 @@ begin
elsif rising_edge(clk_i) then
res_o <= (others => '0'); -- default
if (valid = '1') then
res_o <= res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or res_out(op_cz_c) or
res_out(op_cpop_c) or res_out(op_max_c) or res_out(op_sext_c) or res_out(op_zexth_c) or
res_out(op_rot_c) or res_out(op_orcb_c) or res_out(op_rev8_c) or res_out(op_shadd_c) or
res_out(op_bclr_c) or res_out(op_bext_c) or res_out(op_binv_c) or res_out(op_bset_c) or
res_out(op_pack_c) or res_out(op_zip_c) or res_out(op_brev8_c);
res_o <= res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or res_out(op_cz_c) or
res_out(op_cpop_c) or res_out(op_max_c) or res_out(op_sext_c) or res_out(op_zexth_c) or
res_out(op_rot_c) or res_out(op_orcb_c) or res_out(op_rev8_c) or res_out(op_shadd_c) or
res_out(op_bclr_c) or res_out(op_bext_c) or res_out(op_binv_c) or res_out(op_bset_c) or
res_out(op_pack_c) or res_out(op_zip_c) or res_out(op_brev8_c) or res_out(op_clmul_c);
end if;
end if;
end process output_gate;

3
rtl/core/neorv32_package.vhd
View file

@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100406"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100407"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width
@ -683,6 +683,7 @@ package neorv32_package is
CPU_EXTENSION_RISCV_M : boolean := false;
CPU_EXTENSION_RISCV_U : boolean := false;
CPU_EXTENSION_RISCV_Zbkb : boolean := false;
CPU_EXTENSION_RISCV_Zbkc : boolean := false;
CPU_EXTENSION_RISCV_Zbkx : boolean := false;
CPU_EXTENSION_RISCV_Zfinx : boolean := false;
CPU_EXTENSION_RISCV_Zicntr : boolean := true;

6
rtl/core/neorv32_top.vhd
View file

@ -39,9 +39,10 @@ entity neorv32_top is
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkb : boolean := false; -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkb : boolean := false; -- implement bit-manipulation instructions for cryptography?
CPU_EXTENSION_RISCV_Zbkc : boolean := false; -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx : boolean := false; -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)?
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
CPU_EXTENSION_RISCV_Zicond : boolean := false; -- implement integer conditional operations?
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
@ -455,6 +456,7 @@ begin
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M,
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U,
CPU_EXTENSION_RISCV_Zbkb => CPU_EXTENSION_RISCV_Zbkb,
CPU_EXTENSION_RISCV_Zbkc => CPU_EXTENSION_RISCV_Zbkc,
CPU_EXTENSION_RISCV_Zbkx => CPU_EXTENSION_RISCV_Zbkx,
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx,
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,

25
rtl/system_integration/neorv32_vivado_ip.tcl
View file

@ -160,6 +160,8 @@ set_property display_name {NEORV32 Zxcfu ISA extension} [ipgu
set_property tooltip {Custom-instructions unit} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zxcfu" -component [ipx::current_core]]
set_property display_name {RISC-V Zbkb ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkb" -component [ipx::current_core]]
set_property tooltip {Bit manipulation instructions for cryptography} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkb" -component [ipx::current_core]]
set_property display_name {RISC-V Zbkc ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkc" -component [ipx::current_core]]
set_property tooltip {Carry-less multiply instr. for cryptography} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkc" -component [ipx::current_core]]
set_property display_name {RISC-V Zbkx ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkx" -component [ipx::current_core]]
set_property tooltip {Scalar cryptographic - crossbar permutations} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkx" -component [ipx::current_core]]
set_property display_name {RISC-V Zknd ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zknd" -component [ipx::current_core]]
@ -197,17 +199,18 @@ ipgui::move_param -component [ipx::current_core] -order 11 [ipgui::get_guiparams
ipgui::move_param -component [ipx::current_core] -order 12 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zmmul" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 13 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zxcfu" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 14 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkb" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 15 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkx" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 16 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zknd" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 17 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zkne" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 18 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zknh" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 19 [ipgui::get_guiparamspec -name "FAST_MUL_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 20 [ipgui::get_guiparamspec -name "FAST_SHIFT_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 21 [ipgui::get_guiparamspec -name "REGFILE_HW_RST" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 22 [ipgui::get_guiparamspec -name "PMP_NUM_REGIONS" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 23 [ipgui::get_guiparamspec -name "PMP_MIN_GRANULARITY" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 24 [ipgui::get_guiparamspec -name "PMP_TOR_MODE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 25 [ipgui::get_guiparamspec -name "PMP_NAP_MODE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 15 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkc" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 16 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zbkx" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 17 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zknd" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 18 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zkne" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 19 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zknh" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 20 [ipgui::get_guiparamspec -name "FAST_MUL_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 21 [ipgui::get_guiparamspec -name "FAST_SHIFT_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 22 [ipgui::get_guiparamspec -name "REGFILE_HW_RST" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 23 [ipgui::get_guiparamspec -name "PMP_NUM_REGIONS" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 24 [ipgui::get_guiparamspec -name "PMP_MIN_GRANULARITY" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 25 [ipgui::get_guiparamspec -name "PMP_TOR_MODE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
ipgui::move_param -component [ipx::current_core] -order 26 [ipgui::get_guiparamspec -name "PMP_NAP_MODE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
# **************************************************************

2
rtl/system_integration/neorv32_vivado_ip.vhd
View file

@ -42,6 +42,7 @@ entity neorv32_vivado_ip is
CPU_EXTENSION_RISCV_M : boolean := false;
CPU_EXTENSION_RISCV_U : boolean := false;
CPU_EXTENSION_RISCV_Zbkb : boolean := false;
CPU_EXTENSION_RISCV_Zbkc : boolean := false;
CPU_EXTENSION_RISCV_Zbkx : boolean := false;
CPU_EXTENSION_RISCV_Zfinx : boolean := false;
CPU_EXTENSION_RISCV_Zicntr : boolean := false;
@ -312,6 +313,7 @@ begin
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M,
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U,
CPU_EXTENSION_RISCV_Zbkb => CPU_EXTENSION_RISCV_Zbkb,
CPU_EXTENSION_RISCV_Zbkc => CPU_EXTENSION_RISCV_Zbkc,
CPU_EXTENSION_RISCV_Zbkx => CPU_EXTENSION_RISCV_Zbkx,
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx,
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,

1
sim/neorv32_tb.vhd
View file

@ -207,6 +207,7 @@ begin
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkb => true, -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkc => true, -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx => true, -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?

1
sim/simple/neorv32_tb.simple.vhd
View file

@ -179,6 +179,7 @@ begin
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkb => true, -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkc => true, -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx => true, -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?

2
sw/example/processor_check/makefile
View file

@ -1,7 +1,7 @@
# Override default configuration
override GHDL_RUN_FLAGS ?= --stop-time=15ms
override EFFORT = -Os
override MARCH = rv32ima_zba_zbb_zbs_zbkb_zbkx_zknd_zkne_zknh_zicsr_zfinx_zifencei_zicond
override MARCH = rv32ima_zba_zbb_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zicsr_zfinx_zifencei_zicond
override USER_FLAGS += -flto -Wl,--defsym,__neorv32_heap_size=3096
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)

1
sw/lib/include/neorv32_cpu_csr.h
View file

@ -324,6 +324,7 @@ enum NEORV32_CSR_XISA_enum {
CSR_MXISA_ZKNE = 14, /**< CPU mxisa CSR (14): scalar cryptography - NIST AES encryption (r/-)*/
CSR_MXISA_ZKNH = 15, /**< CPU mxisa CSR (15): scalar cryptography - NIST hash functions (r/-)*/
CSR_MXISA_ZBKB = 16, /**< CPU mxisa CSR (16): scalar cryptography - bit manipulation instructions (r/-)*/
CSR_MXISA_ZBKC = 17, /**< CPU mxisa CSR (17): scalar cryptography - carry-less multiplication instructions (r/-)*/
// Misc
CSR_MXISA_IS_SIM = 20, /**< CPU mxisa CSR (20): this might be a simulation when set (r/-)*/

1
sw/lib/source/neorv32_rte.c
View file

@ -451,6 +451,7 @@ void neorv32_rte_print_hw_config(void) {
if (tmp & (1<<CSR_MXISA_SDTRIG)) { neorv32_uart0_printf("Sdtrig "); }
if (tmp & (1<<CSR_MXISA_SMPMP)) { neorv32_uart0_printf("Smpmp "); }
if (tmp & (1<<CSR_MXISA_ZBKB)) { neorv32_uart0_printf("Zbkb "); }
if (tmp & (1<<CSR_MXISA_ZBKC)) { neorv32_uart0_printf("Zbkc "); }
if (tmp & (1<<CSR_MXISA_ZBKX)) { neorv32_uart0_printf("Zbkx "); }
if (tmp & (1<<CSR_MXISA_ZFINX)) { neorv32_uart0_printf("Zfinx "); }
if (tmp & (1<<CSR_MXISA_ZICNTR)) { neorv32_uart0_printf("Zicntr "); }