mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-24 06:07:52 -04:00
[sw] add legacy compatibility wrapper library
This commit is contained in:
stnolting
parent
084bcbbe4a
commit
a6614e0244
3 changed files with 123 additions and 54 deletions
|
|
@ -94,7 +94,8 @@ The NEORV32 project provides a set of pre-defined C libraries that allow an easy
|
|||
| `neorv32_dma.c` | `neorv32_dma.h` | <<_direct_memory_access_controller_dma>> HAL
|
||||
| `neorv32_gpio.c` | `neorv32_gpio.h` | <<_general_purpose_input_and_output_port_gpio>> HAL
|
||||
| `neorv32_gptmr.c` | `neorv32_gptmr.h` | <<_general_purpose_timer_gptmr>> HAL
|
||||
| - | `neorv32_intrinsics.h` | Macros for intrinsics & custom instructions
|
||||
| - | `neorv32_intrinsics.h` | Macros for intrinsics and custom instructions
|
||||
| - | `neorv32_legacy.h` | Legacy compatibility layer / wrappers (**do not use for new designs!**)
|
||||
| `neorv32_mtime.c` | `neorv32_mtime.h` | <<_machine_system_timer_mtime>> HAL
|
||||
| `neorv32_neoled.c` | `neorv32_neoled.h` | <<_smart_led_interface_neoled>> HAL
|
||||
| `neorv32_onewire.c` | `neorv32_onewire.h` | <<_one_wire_serial_interface_controller_onewire>> HAL
|
||||
|
|
|
|||
|
|
@ -23,24 +23,60 @@ extern "C" {
|
|||
// Standard libraries
|
||||
#include <stdint.h>
|
||||
#include <inttypes.h>
|
||||
#include <limits.h>
|
||||
#include <unistd.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Processor clock prescaler select
|
||||
* @name Main Address Space Sections
|
||||
**************************************************************************/
|
||||
enum NEORV32_CLOCK_PRSC_enum {
|
||||
CLK_PRSC_2 = 0, /**< CPU_CLK (from clk_i top signal) / 2 */
|
||||
CLK_PRSC_4 = 1, /**< CPU_CLK (from clk_i top signal) / 4 */
|
||||
CLK_PRSC_8 = 2, /**< CPU_CLK (from clk_i top signal) / 8 */
|
||||
CLK_PRSC_64 = 3, /**< CPU_CLK (from clk_i top signal) / 64 */
|
||||
CLK_PRSC_128 = 4, /**< CPU_CLK (from clk_i top signal) / 128 */
|
||||
CLK_PRSC_1024 = 5, /**< CPU_CLK (from clk_i top signal) / 1024 */
|
||||
CLK_PRSC_2048 = 6, /**< CPU_CLK (from clk_i top signal) / 2048 */
|
||||
CLK_PRSC_4096 = 7 /**< CPU_CLK (from clk_i top signal) / 4096 */
|
||||
};
|
||||
/**@{*/
|
||||
/** XIP-mapped memory base address */
|
||||
#define XIP_MEM_BASE_ADDRESS (0xE0000000U)
|
||||
/** bootloader memory base address */
|
||||
#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U)
|
||||
/** peripheral/IO devices memory base address */
|
||||
#define IO_BASE_ADDRESS (0xFFFFE000U)
|
||||
/**@}*/
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* @name IO Address Space Map - Peripheral/IO Devices
|
||||
**************************************************************************/
|
||||
/**@{*/
|
||||
//#define NEORV32_???_BASE (0xFFFFE000U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE100U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE200U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE300U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE400U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE500U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE600U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE700U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE800U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFE900U) /**< reserved */
|
||||
//#define NEORV32_???_BASE (0xFFFFEA00U) /**< reserved */
|
||||
#define NEORV32_CFS_BASE (0xFFFFEB00U) /**< Custom Functions Subsystem (CFS) */
|
||||
#define NEORV32_SLINK_BASE (0xFFFFEC00U) /**< Stream Link Interface (SLINK) */
|
||||
#define NEORV32_DMA_BASE (0xFFFFED00U) /**< Direct Memory Access Controller (DMA) */
|
||||
#define NEORV32_CRC_BASE (0xFFFFEE00U) /**< Cyclic Redundancy Check Unit (DMA) */
|
||||
#define NEORV32_XIP_BASE (0xFFFFEF00U) /**< Execute In Place Module (XIP) */
|
||||
#define NEORV32_PWM_BASE (0xFFFFF000U) /**< Pulse Width Modulation Controller (PWM) */
|
||||
#define NEORV32_GPTMR_BASE (0xFFFFF100U) /**< General Purpose Timer (GPTMR) */
|
||||
#define NEORV32_ONEWIRE_BASE (0xFFFFF200U) /**< 1-Wire Interface Controller (ONEWIRE) */
|
||||
#define NEORV32_XIRQ_BASE (0xFFFFF300U) /**< External Interrupt Controller (XIRQ) */
|
||||
#define NEORV32_MTIME_BASE (0xFFFFF400U) /**< Machine System Timer (MTIME) */
|
||||
#define NEORV32_UART0_BASE (0xFFFFF500U) /**< Primary Universal Asynchronous Receiver and Transmitter (UART0) */
|
||||
#define NEORV32_UART1_BASE (0xFFFFF600U) /**< Secondary Universal Asynchronous Receiver and Transmitter (UART1) */
|
||||
#define NEORV32_SDI_BASE (0xFFFFF700U) /**< Serial Data Interface (SDI) */
|
||||
#define NEORV32_SPI_BASE (0xFFFFF800U) /**< Serial Peripheral Interface Controller (SPI) */
|
||||
#define NEORV32_TWI_BASE (0xFFFFF900U) /**< Two-Wire Interface Controller (TWI) */
|
||||
#define NEORV32_TRNG_BASE (0xFFFFFA00U) /**< True Random Number Generator (TRNG) */
|
||||
#define NEORV32_WDT_BASE (0xFFFFFB00U) /**< Watchdog Timer (WDT) */
|
||||
#define NEORV32_GPIO_BASE (0xFFFFFC00U) /**< General Purpose Input/Output Port Controller (GPIO) */
|
||||
#define NEORV32_NEOLED_BASE (0xFFFFFD00U) /**< Smart LED Hardware Interface (NEOLED) */
|
||||
#define NEORV32_SYSINFO_BASE (0xFFFFFE00U) /**< System Information Memory (SYSINFO) */
|
||||
#define NEORV32_DM_BASE (0xFFFFFF00U) /**< On-Chip Debugger - Debug Module (OCD) */
|
||||
/**@}*/
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
|
|
@ -153,47 +189,6 @@ enum NEORV32_CLOCK_PRSC_enum {
|
|||
/**@}*/
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* @name Main Address Space Sections
|
||||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** XIP-mapped memory base address */
|
||||
#define XIP_MEM_BASE_ADDRESS (0xE0000000U)
|
||||
/** bootloader memory base address */
|
||||
#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U)
|
||||
/** peripheral/IO devices memory base address */
|
||||
#define IO_BASE_ADDRESS (0xFFFFE000U)
|
||||
/**@}*/
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* @name IO Address Space - Peripheral/IO Devices
|
||||
**************************************************************************/
|
||||
/**@{*/
|
||||
#define NEORV32_CFS_BASE (0xFFFFEB00U) /**< Custom Functions Subsystem (CFS) */
|
||||
#define NEORV32_SLINK_BASE (0xFFFFEC00U) /**< Stream Link Interface (SLINK) */
|
||||
#define NEORV32_DMA_BASE (0xFFFFED00U) /**< Direct Memory Access Controller (DMA) */
|
||||
#define NEORV32_CRC_BASE (0xFFFFEE00U) /**< Cyclic Redundancy Check Unit (DMA) */
|
||||
#define NEORV32_XIP_BASE (0xFFFFEF00U) /**< Execute In Place Module (XIP) */
|
||||
#define NEORV32_PWM_BASE (0xFFFFF000U) /**< Pulse Width Modulation Controller (PWM) */
|
||||
#define NEORV32_GPTMR_BASE (0xFFFFF100U) /**< General Purpose Timer (GPTMR) */
|
||||
#define NEORV32_ONEWIRE_BASE (0xFFFFF200U) /**< 1-Wire Interface Controller (ONEWIRE) */
|
||||
#define NEORV32_XIRQ_BASE (0xFFFFF300U) /**< External Interrupt Controller (XIRQ) */
|
||||
#define NEORV32_MTIME_BASE (0xFFFFF400U) /**< Machine System Timer (MTIME) */
|
||||
#define NEORV32_UART0_BASE (0xFFFFF500U) /**< Primary Universal Asynchronous Receiver and Transmitter (UART0) */
|
||||
#define NEORV32_UART1_BASE (0xFFFFF600U) /**< Secondary Universal Asynchronous Receiver and Transmitter (UART1) */
|
||||
#define NEORV32_SDI_BASE (0xFFFFF700U) /**< Serial Data Interface (SDI) */
|
||||
#define NEORV32_SPI_BASE (0xFFFFF800U) /**< Serial Peripheral Interface Controller (SPI) */
|
||||
#define NEORV32_TWI_BASE (0xFFFFF900U) /**< Two-Wire Interface Controller (TWI) */
|
||||
#define NEORV32_TRNG_BASE (0xFFFFFA00U) /**< True Random Number Generator (TRNG) */
|
||||
#define NEORV32_WDT_BASE (0xFFFFFB00U) /**< Watchdog Timer (WDT) */
|
||||
#define NEORV32_GPIO_BASE (0xFFFFFC00U) /**< General Purpose Input/Output Port Controller (GPIO) */
|
||||
#define NEORV32_NEOLED_BASE (0xFFFFFD00U) /**< Smart LED Hardware Interface (NEOLED) */
|
||||
#define NEORV32_SYSINFO_BASE (0xFFFFFE00U) /**< System Information Memory (SYSINFO) */
|
||||
#define NEORV32_DM_BASE (0xFFFFFF00U) /**< On-Chip Debugger - Debug Module (OCD) */
|
||||
/**@}*/
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Include all system header files
|
||||
// ----------------------------------------------------------------------------
|
||||
|
|
@ -203,6 +198,9 @@ enum NEORV32_CLOCK_PRSC_enum {
|
|||
// helper functions
|
||||
#include "neorv32_aux.h"
|
||||
|
||||
// legacy compatibility layer
|
||||
#include "neorv32_legacy.h"
|
||||
|
||||
// cpu core
|
||||
#include "neorv32_cpu.h"
|
||||
#include "neorv32_cpu_amo.h"
|
||||
|
|
|
|||
70
sw/lib/include/neorv32_legacy.h
Normal file
70
sw/lib/include/neorv32_legacy.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
// ================================================================================ //
|
||||
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
|
||||
// Copyright (c) NEORV32 contributors. //
|
||||
// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //
|
||||
// Licensed under the BSD-3-Clause license, see LICENSE for details. //
|
||||
// SPDX-License-Identifier: BSD-3-Clause //
|
||||
// ================================================================================ //
|
||||
|
||||
/**
|
||||
* @file neorv32_legacy.h
|
||||
* @brief Legacy compatibility layer.
|
||||
* @warning Deprecated! Do not use for new designs!
|
||||
* @see https://stnolting.github.io/neorv32/sw/files.html
|
||||
*/
|
||||
|
||||
#ifndef neorv32_legacy_h
|
||||
#define neorv32_legacy_h
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* @name UART0 legacy compatibility wrappers
|
||||
**************************************************************************/
|
||||
/**@{*/
|
||||
#define neorv32_uart0_available() neorv32_uart_available(NEORV32_UART0)
|
||||
#define neorv32_uart0_get_rx_fifo_depth() neorv32_uart_get_rx_fifo_depth(NEORV32_UART0)
|
||||
#define neorv32_uart0_get_tx_fifo_depth() neorv32_uart_get_tx_fifo_depth(NEORV32_UART0)
|
||||
#define neorv32_uart0_setup(baudrate, irq_mask) neorv32_uart_setup(NEORV32_UART0, baudrate, irq_mask)
|
||||
#define neorv32_uart0_disable() neorv32_uart_disable(NEORV32_UART0)
|
||||
#define neorv32_uart0_enable() neorv32_uart_enable(NEORV32_UART0)
|
||||
#define neorv32_uart0_rtscts_disable() neorv32_uart_rtscts_disable(NEORV32_UART0)
|
||||
#define neorv32_uart0_rtscts_enable() neorv32_uart_rtscts_enable(NEORV32_UART0)
|
||||
#define neorv32_uart0_putc(c) neorv32_uart_putc(NEORV32_UART0, c)
|
||||
#define neorv32_uart0_rx_clear() neorv32_uart_rx_clear(NEORV32_UART0)
|
||||
#define neorv32_uart0_tx_clear() neorv32_uart_tx_clear(NEORV32_UART0)
|
||||
#define neorv32_uart0_tx_busy() neorv32_uart_tx_busy(NEORV32_UART0)
|
||||
#define neorv32_uart0_getc() neorv32_uart_getc(NEORV32_UART0)
|
||||
#define neorv32_uart0_char_received() neorv32_uart_char_received(NEORV32_UART0)
|
||||
#define neorv32_uart0_char_received_get() neorv32_uart_char_received_get(NEORV32_UART0)
|
||||
#define neorv32_uart0_puts(s) neorv32_uart_puts(NEORV32_UART0, s)
|
||||
#define neorv32_uart0_printf(...) neorv32_uart_printf(NEORV32_UART0, __VA_ARGS__)
|
||||
#define neorv32_uart0_scan(buffer, max_size, echo) neorv32_uart_scan(NEORV32_UART0, buffer, max_size, echo)
|
||||
/**@}*/
|
||||
|
||||
/**********************************************************************//**
|
||||
* @name UART1 legacy compatibility wrappers
|
||||
**************************************************************************/
|
||||
/**@{*/
|
||||
#define neorv32_uart1_available() neorv32_uart_available(NEORV32_UART1)
|
||||
#define neorv32_uart1_get_rx_fifo_depth() neorv32_uart_get_rx_fifo_depth(NEORV32_UART1)
|
||||
#define neorv32_uart1_get_tx_fifo_depth() neorv32_uart_get_tx_fifo_depth(NEORV32_UART1)
|
||||
#define neorv32_uart1_setup(baudrate, irq_mask) neorv32_uart_setup(NEORV32_UART1, baudrate, irq_mask)
|
||||
#define neorv32_uart1_disable() neorv32_uart_disable(NEORV32_UART1)
|
||||
#define neorv32_uart1_enable() neorv32_uart_enable(NEORV32_UART1)
|
||||
#define neorv32_uart1_rtscts_disable() neorv32_uart_rtscts_disable(NEORV32_UART1)
|
||||
#define neorv32_uart1_rtscts_enable() neorv32_uart_rtscts_enable(NEORV32_UART1)
|
||||
#define neorv32_uart1_putc(c) neorv32_uart_putc(NEORV32_UART1, c)
|
||||
#define neorv32_uart1_rx_clear() neorv32_uart_rx_clear(NEORV32_UART1)
|
||||
#define neorv32_uart1_tx_clear() neorv32_uart_tx_clear(NEORV32_UART1)
|
||||
#define neorv32_uart1_tx_busy() neorv32_uart_tx_busy(NEORV32_UART1)
|
||||
#define neorv32_uart1_getc() neorv32_uart_getc(NEORV32_UART1)
|
||||
#define neorv32_uart1_char_received() neorv32_uart_char_received(NEORV32_UART1)
|
||||
#define neorv32_uart1_char_received_get() neorv32_uart_char_received_get(NEORV32_UART1)
|
||||
#define neorv32_uart1_puts(s) neorv32_uart_puts(NEORV32_UART1, s)
|
||||
#define neorv32_uart1_printf(...) neorv32_uart_printf(NEORV32_UART1, __VA_ARGS__)
|
||||
#define neorv32_uart1_scan(buffer, max_size, echo) neorv32_uart_scan(NEORV32_UART1, buffer, max_size, echo)
|
||||
/**@}*/
|
||||
|
||||
#endif // neorv32_legacy_h
|
||||
Loading…
Add table
Add a link
Reference in a new issue