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Add NEORV32 as Vivado IP (#894)
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10 changed files with 914 additions and 659 deletions
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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| Date | Version | Comment | Ticket |
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|:----:|:-------:|:--------|:------:|
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| 04.05.2024 | 1.9.9.1 | :sparkles: add NEORV32 as Vivado IP block | [#894](https://github.com/stnolting/neorv32/pull/894) |
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| 03.05.2024 | [**:rocket:1.9.9**](https://github.com/stnolting/neorv32/releases/tag/v1.9.9) | **New release** | |
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| 02.05.2024 | 1.9.8.10 | :bug: fix UART receiver bug (introduced in v1.9.8.7) | [#891](https://github.com/stnolting/neorv32/pull/891) |
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| 01.05.2024 | 1.9.8.9 | minor rtl cleanups (cleanup boolean expressions) | [#889](https://github.com/stnolting/neorv32/pull/889) |
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docs/figures/vivado_ip_gui.png
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docs/figures/vivado_ip_soc.png
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@ -22,7 +22,7 @@ which provides **SoC setups** for various FPGAs, boards and toolchains.
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* <<_application_specific_processor_configuration, optimizing>> the core for your application
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* add <<_adding_custom_hardware_modules, custom hardware extensions>> and <<_customizing_the_internal_bootloader, customizing the bootloader>>
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* <<_programming_an_external_spi_flash_via_the_bootloader, program>> an external SPI flash for persistent application storage
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* generate a Xilinx Vivado <<_packaging_the_processor_as_ip_block_for_xilinx_vivado_block_designer, IP block>>
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* generate an AMD Vivado <<_packaging_the_processor_as_vivado_ip_block, IP block>>
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* <<_simulating_the_processor, simulate>> the processor and <<_building_the_documentation, build the documentation>>
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* RTOS support for <<_zephyr_rtos_support, Zephyr>> and <<_freertos_support, FreeRTOS>>
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* build SoCs using <<_litex_soc_builder_support, LiteX>>
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@ -1,45 +1,45 @@
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<<<
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:sectnums:
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== Packaging the Processor as IP block for Xilinx Vivado Block Designer
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== Packaging the Processor as Vivado IP Block
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Packaging the entire processor as IP module allows easy integration of the core (or even several cores)
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into a block-design-based Vivado project. The NEORV32 repository provides a full-scale TCL script that
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automatically packages the processor as IP block.
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.Example Vivado SoC using the NEORV32 IP Block
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image::vivado_ip_soc.png[]
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Besides packaging the HDL modules, the TCL script also generates a simplified customization GUI that enables
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configuration of the processor. The rather complex VHDL configuration generics are renamed and provided with tool tips
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to make it easier to understand the options.
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.NEORV32 IP Customization GUI
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image::vivado_ip_gui.png[]
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The following steps show how to package the processor using the provided TCL script and how to import
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the generated IP block into the Vivado IP repository.
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[start=1]
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. Import all the core files from `rtl/core` (including default internal memory architectures from `rtl/core/mem`)
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and assign them to a _new_ design library `neorv32`.
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. Instantiate the `rtl/system_integration/neorv32_top_axi4lite.vhd` module.
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. Then either directly use that module in a new block-design ("Create Block Design", right-click -> "Add Module",
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thats easier for a first try) or package it ("Tools", "Create and Package new IP") for the use in other projects.
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. Connect your AXI-peripheral directly to the core's AXI4-Interface if you only have one, or to an AXI-Interconnect
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(from the IP-catalog) if you have multiple peripherals.
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. Connect ALL the `ACLK` and `ARESETN` pins of all peripherals and interconnects to the processor's clock and reset
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signals to have a _unified_ clock and reset domain (easier for a first setup).
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. Open the "Address Editor" tab and let Vivado assign the base-addresses for the AXI-peripherals (you can modify them
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according to your needs).
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. For all FPGA-external signals (like UART signals) make all the connections you need "external"
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(right-click on the signal/pin -> "Make External").
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. Save everything, let VIVADO create a HDL-Wrapper for the block-design and choose this as your _Top Level Design_.
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. Define your constraints and generate your bitstream.
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. Open the Vivado GUI.
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. In GUI mode select either "Tools -> Run TCL Script" to directly execute the script or open the TCL
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shell ("Window -> Tcl Console") to manually invoke the script.
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. Use `cd` in the TCL console to navigate to the project's `neorv32/rtl/system_integration` folder.
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. Execute `source source neorv32_vivado_ip.tcl` in the TCL console.
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. A second Vivado instance will open automatically packaging the IP module. After this process is completed,
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the second Vivado instance will automatically close again.
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. A new folder `neorv32_vivado_ip_work` is created in `neorv32/rtl/system_integration` which contains the IP-packaging
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Vivado project.
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. Inside, the `packaged_ip` folder provides the actual IP module.
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. Open your design project in Vivado.
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. Click on "Settings" in the "Project Manager" on the left side.
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. Under "Project Settings" expand the "IP" section and click on "Repository".
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. Click the large plus button and select the previously generated IP folder (`path/to/neorv32/rtl/system_integration/neorv32_vivado_ip_work/packaged_ip`).
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. Click "Select" and close the Settings menu with "Apply" and "OK".
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. You will find the NEORV32 in the "User Repository" section of the Vivado IP catalog.
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.Example AXI SoC using Xilinx Vivado
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image::neorv32_axi_soc.png[]
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.True Random Number Generator
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[IMPORTANT]
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The NEORV32 TRNG peripheral is enabled by default in the `neorv32_top_axi4lite` AXI wrapper. Otherwise, Vivado
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cannot insert the wrapper into a block design (see https://github.com/stnolting/neorv32/issues/227.).
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footnote:[Seems like Vivado has problem evaluating design source files that have more than two in-file sub-entities.]
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If the TRNG is not needed, you can disable it by double-clicking on the module's block and de-selecting
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"IO_TRNG_EN" after inserting the module.
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.SLINK AXI4-Stream Interfaces
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[IMPORTANT]
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The SLINK peripheral's input and output streams are exposed as AXI4-Stream compatible interfaces in the
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`rtl/system_integration/neorv32_top_axi4lite.vhd` top-level module. These interfaces provide clock inputs for
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each of the streams, so that they can be connected to an appropriate clock source to satisfy Vivado's
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validation for compatible clocks on each end of the stream connection. However, these clock inputs are not presently
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used internally to the core, and using streams clocked on a clock domain other than that connected to m_axi_aclk is NOT
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presently supported - doing this will result in timing failures or improper operation.
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**Combinatorial Loops DRC error**
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.Combinatorial Loops DRC Errors
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[WARNING]
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If the TRNG is enabled it is recommended to add the following commands to the project's constraints file in order
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to prevent DRC errors during bitstream generation:
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@ -49,7 +49,3 @@ set_property SEVERITY {warning} [get_drc_checks LUTLP-1]
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set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]
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set_property ALLOW_COMBINATORIAL_LOOPS TRUE
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----
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[NOTE]
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Guide provided by GitHub user https://github.com/AWenzel83[`AWenzel83`] (see
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https://github.com/stnolting/neorv32/discussions/52#discussioncomment-819013). ❤️
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@ -29,7 +29,7 @@ package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090900"; -- hardware version
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090901"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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constant XLEN : natural := 32; -- native data path width
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@ -1,617 +0,0 @@
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-- ================================================================================ --
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-- NEORV32 - Processor Top Entity with AXI4-Lite & AXI4-Stream Compatible Interface --
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-- -------------------------------------------------------------------------------- --
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-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
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-- Copyright (c) NEORV32 contributors. --
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-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
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-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
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-- SPDX-License-Identifier: BSD-3-Clause --
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-- ================================================================================ --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_SystemTop_axi4lite is
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generic (
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-- ------------------------------------------------------------
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-- Configuration Generics --
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-- ------------------------------------------------------------
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
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JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000"; -- JEDEC ID: continuation codes + vendor ID
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INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic memory operations extension?
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
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CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16)
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PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
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-- Atomic Memory Access - Reservation Set Granularity --
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AMO_RVS_GRANULARITY : natural := 4; -- size in bytes, has to be a power of 2, min 4
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-- Internal Instruction memory --
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MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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-- Internal Data memory --
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MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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-- Internal Cache memory --
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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-- Internal Data Cache (dCACHE) --
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DCACHE_EN : boolean := false; -- implement data cache
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DCACHE_NUM_BLOCKS : natural := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
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DCACHE_BLOCK_SIZE : natural := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
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-- Execute in-place module (XIP) --
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XIP_EN : boolean := false; -- implement execute in place module (XIP)?
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XIP_CACHE_EN : boolean := false; -- implement XIP cache?
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XIP_CACHE_NUM_BLOCKS : natural range 1 to 256 := 8; -- number of blocks (min 1), has to be a power of 2
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XIP_CACHE_BLOCK_SIZE : natural range 1 to 2**16 := 256; -- block size in bytes (min 4), has to be a power of 2
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-- External Interrupts Controller (XIRQ) --
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XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
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XIRQ_TRIGGER_TYPE : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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-- Processor peripherals --
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IO_GPIO_NUM : natural := 0; -- number of GPIO input/output pairs (0..64)
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IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_FIFO : natural := 1; -- SPI RTX fifo depth, has to be a power of two, min 1
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IO_SDI_EN : boolean := false; -- implement serial data interface (SDI)?
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IO_SDI_FIFO : natural := 1; -- RTX fifo depth, has to be zero or a power of two, min 1
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IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..12); 0 = disabled
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IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
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IO_TRNG_FIFO : natural := 1; -- TRNG fifo depth, has to be a power of two, min 1
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
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IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)?
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IO_DMA_EN : boolean := false; -- implement direct memory access controller (DMA)?
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IO_SLINK_EN : boolean := false; -- implement stream link interface (SLINK)?
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IO_SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_CRC_EN : boolean := false -- implement cyclic redundancy check unit (CRC)?
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);
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port (
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-- ------------------------------------------------------------
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-- AXI4-Lite-Compatible Master Interface --
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-- ------------------------------------------------------------
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-- Clock and Reset --
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m_axi_aclk : in std_logic;
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m_axi_aresetn : in std_logic;
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-- Write Address Channel --
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m_axi_awaddr : out std_logic_vector(31 downto 0);
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m_axi_awprot : out std_logic_vector(2 downto 0);
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m_axi_awvalid : out std_logic;
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m_axi_awready : in std_logic;
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-- Write Data Channel --
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m_axi_wdata : out std_logic_vector(31 downto 0);
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m_axi_wstrb : out std_logic_vector(3 downto 0);
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m_axi_wvalid : out std_logic;
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m_axi_wready : in std_logic;
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-- Read Address Channel --
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m_axi_araddr : out std_logic_vector(31 downto 0);
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m_axi_arprot : out std_logic_vector(2 downto 0);
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m_axi_arvalid : out std_logic;
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m_axi_arready : in std_logic;
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-- Read Data Channel --
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m_axi_rdata : in std_logic_vector(31 downto 0);
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m_axi_rresp : in std_logic_vector(1 downto 0);
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m_axi_rvalid : in std_logic;
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m_axi_rready : out std_logic;
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-- Write Response Channel --
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m_axi_bresp : in std_logic_vector(1 downto 0);
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m_axi_bvalid : in std_logic;
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m_axi_bready : out std_logic;
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-- ------------------------------------------------------------
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-- AXI4-Stream-Compatible Interface --
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-- ------------------------------------------------------------
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-- Source --
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s0_axis_tdata : out std_logic_vector(31 downto 0);
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s0_axis_tvalid : out std_logic;
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s0_axis_tlast : out std_logic;
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s0_axis_tready : in std_logic;
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s0_axis_aclk : in std_logic; -- present to satisfy Vivado, not used!
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-- Sink --
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s1_axis_tdata : in std_logic_vector(31 downto 0);
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s1_axis_tvalid : in std_logic;
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s1_axis_tlast : in std_logic;
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s1_axis_tready : out std_logic;
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s1_axis_aclk : in std_logic; -- present to satisfy Vivado, not used!
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-- ------------------------------------------------------------
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-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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-- ------------------------------------------------------------
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jtag_trst_i : in std_logic; -- low-active TAP reset (optional)
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jtag_tck_i : in std_logic; -- serial clock
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jtag_tdi_i : in std_logic; -- serial data input
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jtag_tdo_o : out std_logic; -- serial data output
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jtag_tms_i : in std_logic; -- mode select
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-- ------------------------------------------------------------
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-- Processor IO --
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-- ------------------------------------------------------------
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-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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xip_csn_o : out std_logic; -- chip-select, low-active
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xip_clk_o : out std_logic; -- serial clock
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xip_dat_i : in std_logic; -- device data input
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xip_dat_o : out std_logic; -- controller data output
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-- GPIO (available if IO_GPIO_EN = true) --
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gpio_o : out std_logic_vector(63 downto 0); -- parallel output
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gpio_i : in std_logic_vector(63 downto 0); -- parallel input
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart0_txd_o : out std_logic; -- UART0 send data
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uart0_rxd_i : in std_logic; -- UART0 receive data
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uart0_rts_o : out std_logic; -- HW flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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uart0_cts_i : in std_logic; -- HW flow control: UART0.TX allowed to transmit, low-active, optional
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-- secondary UART1 (available if IO_UART1_EN = true) --
|
||||
uart1_txd_o : out std_logic; -- UART1 send data
|
||||
uart1_rxd_i : in std_logic; -- UART1 receive data
|
||||
uart1_rts_o : out std_logic; -- HW flow control: UART1.RX ready to receive ("RTR"), low-active, optional
|
||||
uart1_cts_i : in std_logic; -- HW flow control: UART1.TX allowed to transmit, low-active, optional
|
||||
-- SPI (available if IO_SPI_EN = true) --
|
||||
spi_clk_o : out std_logic; -- SPI serial clock
|
||||
spi_dat_o : out std_logic; -- controller data out, peripheral data in
|
||||
spi_dat_i : in std_logic; -- controller data in, peripheral data out
|
||||
spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS
|
||||
-- SDI (available if IO_SDI_EN = true) --
|
||||
sdi_clk_i : in std_logic; -- SDI serial clock
|
||||
sdi_dat_o : out std_logic; -- controller data out, peripheral data in
|
||||
sdi_dat_i : in std_logic; -- controller data in, peripheral data out
|
||||
sdi_csn_i : in std_logic; -- chip-select
|
||||
-- TWI (available if IO_TWI_EN = true) --
|
||||
twi_sda_i : in std_logic; -- serial data line sense input
|
||||
twi_sda_o : out std_logic; -- serial data line output (pull low only)
|
||||
twi_scl_i : in std_logic; -- serial clock line sense input
|
||||
twi_scl_o : out std_logic; -- serial clock line output (pull low only)
|
||||
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
|
||||
onewire_i : in std_logic; -- 1-wire bus sense input
|
||||
onewire_o : out std_logic; -- 1-wire bus output (pull low only)
|
||||
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
||||
pwm_o : out std_logic_vector(11 downto 0); -- pwm channels
|
||||
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
||||
cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs
|
||||
cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs
|
||||
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
||||
neoled_o : out std_logic; -- async serial data line
|
||||
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
||||
xirq_i : in std_logic_vector(31 downto 0); -- IRQ channels
|
||||
-- CPU Interrupts --
|
||||
mtime_irq_i : in std_logic; -- machine timer interrupt, available if IO_MTIME_EN = false
|
||||
msw_irq_i : in std_logic; -- machine software interrupt
|
||||
mext_irq_i : in std_logic -- machine external interrupt
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_SystemTop_axi4lite_rtl of neorv32_SystemTop_axi4lite is
|
||||
|
||||
-- type conversion --
|
||||
constant IO_CFS_CONFIG_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG);
|
||||
constant XIRQ_TRIGGER_TYPE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_TYPE);
|
||||
constant XIRQ_TRIGGER_POLARITY_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_POLARITY);
|
||||
--
|
||||
signal clk_i_int : std_ulogic;
|
||||
signal rstn_i_int : std_ulogic;
|
||||
--
|
||||
signal s0_axis_tdata_int : std_ulogic_vector(31 downto 0);
|
||||
signal s0_axis_tvalid_int : std_ulogic;
|
||||
signal s0_axis_tlast_int : std_ulogic;
|
||||
signal s0_axis_tready_int : std_ulogic;
|
||||
signal s1_axis_tdata_int : std_ulogic_vector(31 downto 0);
|
||||
signal s1_axis_tvalid_int : std_ulogic;
|
||||
signal s1_axis_tlast_int : std_ulogic;
|
||||
signal s1_axis_tready_int : std_ulogic;
|
||||
--
|
||||
signal jtag_trst_i_int : std_ulogic;
|
||||
signal jtag_tck_i_int : std_ulogic;
|
||||
signal jtag_tdi_i_int : std_ulogic;
|
||||
signal jtag_tdo_o_int : std_ulogic;
|
||||
signal jtag_tms_i_int : std_ulogic;
|
||||
--
|
||||
signal xip_csn_o_int : std_ulogic;
|
||||
signal xip_clk_o_int : std_ulogic;
|
||||
signal xip_dat_i_int : std_ulogic;
|
||||
signal xip_dat_o_int : std_ulogic;
|
||||
--
|
||||
signal gpio_o_int : std_ulogic_vector(63 downto 0);
|
||||
signal gpio_i_int : std_ulogic_vector(63 downto 0);
|
||||
--
|
||||
signal uart0_txd_o_int : std_ulogic;
|
||||
signal uart0_rxd_i_int : std_ulogic;
|
||||
signal uart0_rts_o_int : std_ulogic;
|
||||
signal uart0_cts_i_int : std_ulogic;
|
||||
--
|
||||
signal uart1_txd_o_int : std_ulogic;
|
||||
signal uart1_rxd_i_int : std_ulogic;
|
||||
signal uart1_rts_o_int : std_ulogic;
|
||||
signal uart1_cts_i_int : std_ulogic;
|
||||
--
|
||||
signal spi_clk_o_int : std_ulogic;
|
||||
signal spi_dat_o_int : std_ulogic;
|
||||
signal spi_dat_i_int : std_ulogic;
|
||||
signal spi_csn_o_int : std_ulogic_vector(07 downto 0);
|
||||
--
|
||||
signal pwm_o_int : std_ulogic_vector(11 downto 0);
|
||||
--
|
||||
signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0);
|
||||
signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0);
|
||||
--
|
||||
signal neoled_o_int : std_ulogic;
|
||||
--
|
||||
signal twi_sda_i_int : std_ulogic;
|
||||
signal twi_sda_o_int : std_ulogic;
|
||||
signal twi_scl_i_int : std_ulogic;
|
||||
signal twi_scl_o_int : std_ulogic;
|
||||
--
|
||||
signal onewire_i_int : std_ulogic;
|
||||
signal onewire_o_int : std_ulogic;
|
||||
--
|
||||
signal xirq_i_int : std_ulogic_vector(31 downto 0);
|
||||
--
|
||||
signal mtime_irq_i_int : std_ulogic;
|
||||
signal msw_irq_i_int : std_ulogic;
|
||||
signal mext_irq_i_int : std_ulogic;
|
||||
|
||||
-- internal wishbone bus --
|
||||
type wb_bus_t is record
|
||||
adr : std_ulogic_vector(31 downto 0); -- address
|
||||
di : std_ulogic_vector(31 downto 0); -- processor input data
|
||||
do : std_ulogic_vector(31 downto 0); -- processor output data
|
||||
we : std_ulogic; -- write enable
|
||||
sel : std_ulogic_vector(03 downto 0); -- byte enable
|
||||
stb : std_ulogic; -- strobe
|
||||
cyc : std_ulogic; -- valid cycle
|
||||
ack : std_ulogic; -- transfer acknowledge
|
||||
err : std_ulogic; -- transfer error
|
||||
end record;
|
||||
signal wb_core : wb_bus_t;
|
||||
|
||||
-- AXI bridge control --
|
||||
type ctrl_t is record
|
||||
radr_received : std_ulogic;
|
||||
wadr_received : std_ulogic;
|
||||
wdat_received : std_ulogic;
|
||||
end record;
|
||||
signal ctrl : ctrl_t;
|
||||
|
||||
signal ack_read, ack_write : std_ulogic; -- normal transfer termination
|
||||
signal err_read, err_write : std_ulogic; -- error transfer termination
|
||||
|
||||
begin
|
||||
|
||||
-- The Core Of The Problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_top_inst: neorv32_top
|
||||
generic map (
|
||||
-- General --
|
||||
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
||||
HART_ID => HART_ID, -- hardware thread ID
|
||||
JEDEC_ID => JEDEC_ID, -- vendor's JEDEC ID
|
||||
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
||||
-- On-Chip Debugger (OCD) --
|
||||
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement on-chip debugger
|
||||
DM_LEGACY_MODE => DM_LEGACY_MODE, -- debug module spec version: false = v1.0, true = v0.13
|
||||
-- RISC-V CPU Extensions --
|
||||
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic memory operations extension?
|
||||
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension?
|
||||
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
||||
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
||||
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
|
||||
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
||||
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
||||
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
|
||||
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
|
||||
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
|
||||
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
|
||||
-- Extension Options --
|
||||
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
||||
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
||||
-- Physical Memory Protection (PMP) --
|
||||
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16)
|
||||
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
|
||||
-- Hardware Performance Monitors (HPM) --
|
||||
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29)
|
||||
HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (0..64)
|
||||
-- Atomic Memory Access - Reservation Set Granularity --
|
||||
AMO_RVS_GRANULARITY => AMO_RVS_GRANULARITY, -- size in bytes, has to be a power of 2, min 4
|
||||
-- Internal Instruction memory --
|
||||
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
||||
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
||||
-- Internal Data memory --
|
||||
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
||||
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
||||
-- Internal Cache memory --
|
||||
ICACHE_EN => ICACHE_EN, -- implement instruction cache
|
||||
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2
|
||||
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
||||
-- Internal Data Cache (dCACHE) --
|
||||
DCACHE_EN => DCACHE_EN, -- implement data cache
|
||||
DCACHE_NUM_BLOCKS => DCACHE_NUM_BLOCKS, -- d-cache: number of blocks (min 1), has to be a power of 2
|
||||
DCACHE_BLOCK_SIZE => DCACHE_BLOCK_SIZE, -- d-cache: block size in bytes (min 4), has to be a power of 2
|
||||
-- External bus interface --
|
||||
XBUS_EN => true, -- implement external memory bus interface?
|
||||
XBUS_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled)
|
||||
XBUS_REGSTAGE_EN => true, -- add XBUS register stage
|
||||
-- Execute in-place module (XIP) --
|
||||
XIP_EN => XIP_EN, -- implement execute in place module (XIP)?
|
||||
XIP_CACHE_EN => XIP_CACHE_EN, -- implement XIP cache?
|
||||
XIP_CACHE_NUM_BLOCKS => XIP_CACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2
|
||||
XIP_CACHE_BLOCK_SIZE => XIP_CACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2
|
||||
-- External Interrupts Controller (XIRQ) --
|
||||
XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32)
|
||||
XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE_INT, -- trigger type: 0=level, 1=edge
|
||||
XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
||||
-- Processor peripherals --
|
||||
IO_GPIO_NUM => IO_GPIO_NUM, -- number of GPIO input/output pairs (0..64)
|
||||
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
||||
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
||||
IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
||||
IO_UART0_TX_FIFO => IO_UART0_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1
|
||||
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
||||
IO_UART1_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
||||
IO_UART1_TX_FIFO => IO_UART1_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1
|
||||
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
|
||||
IO_SPI_FIFO => IO_SPI_FIFO, -- SPI RTX fifo depth, has to be a power of two, min 1
|
||||
IO_SDI_EN => IO_SDI_EN, -- implement serial data interface (SDI)?
|
||||
IO_SDI_FIFO => IO_SDI_FIFO, -- RTX fifo depth, has to be zero or a power of two, min 1
|
||||
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
|
||||
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..12); 0 = disabled
|
||||
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
|
||||
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
|
||||
IO_TRNG_FIFO => IO_TRNG_FIFO, -- TRNG fifo depth, has to be a power of two, min 1
|
||||
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
|
||||
IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic
|
||||
IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
|
||||
IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits
|
||||
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
||||
IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
|
||||
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)?
|
||||
IO_ONEWIRE_EN => IO_ONEWIRE_EN, -- implement 1-wire interface (ONEWIRE)?
|
||||
IO_DMA_EN => IO_DMA_EN, -- implement direct memory access controller (DMA)?
|
||||
IO_SLINK_EN => IO_SLINK_EN, -- implement stream link interface (SLINK)?
|
||||
IO_SLINK_RX_FIFO => IO_SLINK_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
||||
IO_SLINK_TX_FIFO => IO_SLINK_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1
|
||||
IO_CRC_EN => IO_CRC_EN -- implement cyclic redundancy check unit (CRC)?
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => clk_i_int, -- global clock, rising edge
|
||||
rstn_i => rstn_i_int, -- global reset, low-active, async
|
||||
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
|
||||
jtag_trst_i => jtag_trst_i_int, -- low-active TAP reset (optional)
|
||||
jtag_tck_i => jtag_tck_i_int, -- serial clock
|
||||
jtag_tdi_i => jtag_tdi_i_int, -- serial data input
|
||||
jtag_tdo_o => jtag_tdo_o_int, -- serial data output
|
||||
jtag_tms_i => jtag_tms_i_int, -- mode select
|
||||
-- External bus interface (available if XBUS_EN = true) --
|
||||
xbus_adr_o => wb_core.adr, -- address
|
||||
xbus_dat_i => wb_core.di, -- read data
|
||||
xbus_dat_o => wb_core.do, -- write data
|
||||
xbus_we_o => wb_core.we, -- read/write
|
||||
xbus_sel_o => wb_core.sel, -- byte enable
|
||||
xbus_stb_o => wb_core.stb, -- strobe
|
||||
xbus_cyc_o => wb_core.cyc, -- valid cycle
|
||||
xbus_ack_i => wb_core.ack, -- transfer acknowledge
|
||||
xbus_err_i => wb_core.err, -- transfer error
|
||||
-- Stream Link Interface (available if IO_SLINK_EN = true) --
|
||||
slink_rx_dat_i => s1_axis_tdata_int, -- RX input data
|
||||
slink_rx_val_i => s1_axis_tvalid_int, -- RX valid input
|
||||
slink_rx_lst_i => s1_axis_tlast_int, -- last element of stream
|
||||
slink_rx_rdy_o => s1_axis_tready_int, -- RX ready to receive
|
||||
slink_tx_dat_o => s0_axis_tdata_int, -- TX output data
|
||||
slink_tx_val_o => s0_axis_tvalid_int, -- TX valid output
|
||||
slink_tx_lst_o => s0_axis_tlast_int, -- last element of stream
|
||||
slink_tx_rdy_i => s0_axis_tready_int, -- TX ready to send
|
||||
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
|
||||
xip_csn_o => xip_csn_o_int, -- chip-select, low-active
|
||||
xip_clk_o => xip_clk_o_int, -- serial clock
|
||||
xip_dat_i => xip_dat_i_int, -- device data input
|
||||
xip_dat_o => xip_dat_o_int, -- controller data output
|
||||
-- GPIO (available if IO_GPIO_NUM > 0) --
|
||||
gpio_o => gpio_o_int, -- parallel output
|
||||
gpio_i => gpio_i_int, -- parallel input
|
||||
-- primary UART0 (available if IO_UART0_EN = true) --
|
||||
uart0_txd_o => uart0_txd_o_int, -- UART0 send data
|
||||
uart0_rxd_i => uart0_rxd_i_int, -- UART0 receive data
|
||||
uart0_rts_o => uart0_rts_o_int, -- HW flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart0_cts_i => uart0_cts_i_int, -- HW flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
-- secondary UART1 (available if IO_UART1_EN = true) --
|
||||
uart1_txd_o => uart1_txd_o_int, -- UART1 send data
|
||||
uart1_rxd_i => uart1_rxd_i_int, -- UART1 receive data
|
||||
uart1_rts_o => uart1_rts_o_int, -- HW flow control: UART1.RX ready to receive ("RTR"), low-active, optional
|
||||
uart1_cts_i => uart1_cts_i_int, -- HW flow control: UART1.TX allowed to transmit, low-active, optional
|
||||
-- SPI (available if IO_SPI_EN = true) --
|
||||
spi_clk_o => spi_clk_o_int, -- SPI serial clock
|
||||
spi_dat_o => spi_dat_o_int, -- controller data out, peripheral data in
|
||||
spi_dat_i => spi_dat_i_int, -- controller data in, peripheral data out
|
||||
spi_csn_o => spi_csn_o_int, -- SPI CS
|
||||
-- TWI (available if IO_TWI_EN = true) --
|
||||
twi_sda_i => twi_sda_i_int, -- serial data line sense input
|
||||
twi_sda_o => twi_sda_o_int, -- serial data line output (pull low only)
|
||||
twi_scl_i => twi_scl_i_int, -- serial clock line sense input
|
||||
twi_scl_o => twi_scl_o_int, -- serial clock line output (pull low only)
|
||||
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
|
||||
onewire_i => onewire_i_int, -- 1-wire bus sense input
|
||||
onewire_o => onewire_o_int, -- 1-wire bus output (pull low only)
|
||||
-- PWM available if IO_PWM_NUM_CH > 0) --
|
||||
pwm_o => pwm_o_int, -- pwm channels
|
||||
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
||||
cfs_in_i => cfs_in_i_int, -- custom inputs
|
||||
cfs_out_o => cfs_out_o_int, -- custom outputs
|
||||
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
||||
neoled_o => neoled_o_int, -- async serial data line
|
||||
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
||||
xirq_i => xirq_i_int, -- IRQ channels
|
||||
-- CPU Interrupts --
|
||||
mtime_irq_i => mtime_irq_i_int, -- machine timer interrupt, available if IO_MTIME_EN = false
|
||||
msw_irq_i => msw_irq_i_int, -- machine software interrupt
|
||||
mext_irq_i => mext_irq_i_int -- machine external interrupt
|
||||
);
|
||||
|
||||
-- type conversion --
|
||||
s0_axis_tdata <= std_logic_vector(s0_axis_tdata_int);
|
||||
s0_axis_tvalid <= std_logic(s0_axis_tvalid_int);
|
||||
s0_axis_tlast <= std_logic(s0_axis_tlast_int);
|
||||
s0_axis_tready_int <= std_ulogic(s0_axis_tready);
|
||||
s1_axis_tdata_int <= std_ulogic_vector(s1_axis_tdata);
|
||||
s1_axis_tvalid_int <= std_ulogic(s1_axis_tvalid);
|
||||
s1_axis_tlast_int <= std_ulogic(s1_axis_tlast);
|
||||
s1_axis_tready <= std_logic(s1_axis_tready_int);
|
||||
|
||||
xip_csn_o <= std_logic(xip_csn_o_int);
|
||||
xip_clk_o <= std_logic(xip_clk_o_int);
|
||||
xip_dat_i_int <= std_ulogic(xip_dat_i);
|
||||
xip_dat_o <= std_logic(xip_dat_o_int);
|
||||
|
||||
gpio_o <= std_logic_vector(gpio_o_int);
|
||||
gpio_i_int <= std_ulogic_vector(gpio_i);
|
||||
|
||||
jtag_trst_i_int <= std_ulogic(jtag_trst_i);
|
||||
jtag_tck_i_int <= std_ulogic(jtag_tck_i);
|
||||
jtag_tdi_i_int <= std_ulogic(jtag_tdi_i);
|
||||
jtag_tdo_o <= std_logic(jtag_tdo_o_int);
|
||||
jtag_tms_i_int <= std_ulogic(jtag_tms_i);
|
||||
|
||||
uart0_txd_o <= std_logic(uart0_txd_o_int);
|
||||
uart0_rxd_i_int <= std_ulogic(uart0_rxd_i);
|
||||
uart0_rts_o <= std_logic(uart0_rts_o_int);
|
||||
uart0_cts_i_int <= std_ulogic(uart0_cts_i);
|
||||
uart1_txd_o <= std_logic(uart1_txd_o_int);
|
||||
uart1_rxd_i_int <= std_ulogic(uart1_rxd_i);
|
||||
uart1_rts_o <= std_logic(uart1_rts_o_int);
|
||||
uart1_cts_i_int <= std_ulogic(uart1_cts_i);
|
||||
|
||||
spi_clk_o <= std_logic(spi_clk_o_int);
|
||||
spi_dat_o <= std_logic(spi_dat_o_int);
|
||||
spi_dat_i_int <= std_ulogic(spi_dat_i);
|
||||
spi_csn_o <= std_logic_vector(spi_csn_o_int);
|
||||
|
||||
pwm_o <= std_logic_vector(pwm_o_int);
|
||||
|
||||
cfs_in_i_int <= std_ulogic_vector(cfs_in_i);
|
||||
cfs_out_o <= std_logic_vector(cfs_out_o_int);
|
||||
|
||||
neoled_o <= std_logic(neoled_o_int);
|
||||
|
||||
twi_sda_i_int <= std_ulogic(twi_sda_i);
|
||||
twi_sda_o <= std_logic(twi_sda_o_int);
|
||||
twi_scl_i_int <= std_ulogic(twi_scl_i);
|
||||
twi_scl_o <= std_logic(twi_scl_o_int);
|
||||
|
||||
onewire_i_int <= std_ulogic(onewire_i);
|
||||
onewire_o <= std_logic(onewire_o_int);
|
||||
|
||||
xirq_i_int <= std_ulogic_vector(xirq_i);
|
||||
|
||||
mtime_irq_i_int <= std_ulogic(mtime_irq_i);
|
||||
msw_irq_i_int <= std_ulogic(msw_irq_i);
|
||||
mext_irq_i_int <= std_ulogic(mext_irq_i);
|
||||
|
||||
|
||||
-- Wishbone to AXI4-Lite Bridge -----------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
-- access arbiter --
|
||||
axi_access_arbiter: process(rstn_i_int, clk_i_int)
|
||||
begin
|
||||
if (rstn_i_int = '0') then
|
||||
ctrl.radr_received <= '0';
|
||||
ctrl.wadr_received <= '0';
|
||||
ctrl.wdat_received <= '0';
|
||||
elsif rising_edge(clk_i_int) then
|
||||
if (wb_core.cyc = '0') then -- idle
|
||||
ctrl.radr_received <= '0';
|
||||
ctrl.wadr_received <= '0';
|
||||
ctrl.wdat_received <= '0';
|
||||
else -- busy
|
||||
-- "read address received" flag --
|
||||
if (wb_core.we = '0') then -- pending READ
|
||||
if (m_axi_arready = '1') then -- read address received by interconnect?
|
||||
ctrl.radr_received <= '1';
|
||||
end if;
|
||||
end if;
|
||||
-- "write address received" flag --
|
||||
if (wb_core.we = '1') then -- pending WRITE
|
||||
if (m_axi_awready = '1') then -- write address received by interconnect?
|
||||
ctrl.wadr_received <= '1';
|
||||
end if;
|
||||
end if;
|
||||
-- "write data received" flag --
|
||||
if (wb_core.we = '1') then -- pending WRITE
|
||||
if (m_axi_wready = '1') then -- write data received by interconnect?
|
||||
ctrl.wdat_received <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process axi_access_arbiter;
|
||||
|
||||
|
||||
-- AXI4-Lite Global Signals --
|
||||
clk_i_int <= std_ulogic(m_axi_aclk);
|
||||
rstn_i_int <= std_ulogic(m_axi_aresetn);
|
||||
|
||||
-- AXI4-Lite Read Address Channel --
|
||||
m_axi_araddr <= std_logic_vector(wb_core.adr);
|
||||
m_axi_arvalid <= std_logic((wb_core.cyc and (not wb_core.we)) and (not ctrl.radr_received));
|
||||
m_axi_arprot <= "000"; -- recommended by AMD
|
||||
|
||||
-- AXI4-Lite Read Data Channel --
|
||||
m_axi_rready <= std_logic(wb_core.cyc and (not wb_core.we));
|
||||
wb_core.di <= std_ulogic_vector(m_axi_rdata);
|
||||
ack_read <= std_ulogic(m_axi_rvalid);
|
||||
err_read <= '0' when (m_axi_rresp = "00") else '1'; -- read response = ok? check this signal only when m_axi_rvalid = '1'
|
||||
|
||||
-- AXI4-Lite Write Address Channel --
|
||||
m_axi_awaddr <= std_logic_vector(wb_core.adr);
|
||||
m_axi_awvalid <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wadr_received));
|
||||
m_axi_awprot <= "000"; -- recommended by AMD
|
||||
|
||||
-- AXI4-Lite Write Data Channel --
|
||||
m_axi_wdata <= std_logic_vector(wb_core.do);
|
||||
m_axi_wvalid <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wdat_received));
|
||||
m_axi_wstrb <= std_logic_vector(wb_core.sel); -- byte-enable
|
||||
|
||||
-- AXI4-Lite Write Response Channel --
|
||||
m_axi_bready <= std_logic(wb_core.cyc and wb_core.we);
|
||||
ack_write <= std_ulogic(m_axi_bvalid);
|
||||
err_write <= '0' when (m_axi_bresp = "00") else '1'; -- write response = ok? check this signal only when m_axi_bvalid = '1'
|
||||
|
||||
-- Wishbone transfer termination --
|
||||
wb_core.ack <= ack_read or ack_write;
|
||||
wb_core.err <= (ack_read and err_read) or (ack_write and err_write);
|
||||
|
||||
|
||||
end architecture;
|
||||
340
rtl/system_integration/neorv32_vivado_ip.tcl
Normal file
340
rtl/system_integration/neorv32_vivado_ip.tcl
Normal file
|
|
@ -0,0 +1,340 @@
|
|||
# -- ================================================================================ --
|
||||
# -- NEORV32 - Vivado IP Packaging + Customization GUI Setup --
|
||||
# -- -------------------------------------------------------------------------------- --
|
||||
# -- This scripts packages the entire processor as Vivado IP module including a fancy --
|
||||
# -- customization GUI. --
|
||||
# -- See the NEORV32 Datasheet and User Guide for more information. --
|
||||
# -- -------------------------------------------------------------------------------- --
|
||||
# -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
|
||||
# -- Copyright (c) NEORV32 contributors. --
|
||||
# -- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
|
||||
# -- Licensed under the BSD-3-Clause license, see LICENSE for details. --
|
||||
# -- SPDX-License-Identifier: BSD-3-Clause --
|
||||
# -- ================================================================================ --
|
||||
|
||||
# **************************************************************
|
||||
# IP configuration
|
||||
# **************************************************************
|
||||
set neorv32_home ../..
|
||||
set rtl_top neorv32_vivado_ip.vhd
|
||||
set logo docs/figures/neorv32_logo_small.png
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Create empty output/working directory
|
||||
# **************************************************************
|
||||
set outputdir neorv32_vivado_ip_work
|
||||
file mkdir $outputdir
|
||||
|
||||
set files [glob -nocomplain "$outputdir/*"]
|
||||
if {[llength $files] != 0} {
|
||||
puts "deleting contents of $outputdir"
|
||||
file delete -force {*}[glob -directory $outputdir *];
|
||||
} else {
|
||||
puts "$outputdir is empty"
|
||||
}
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Create Vivado project
|
||||
# **************************************************************
|
||||
create_project "neorv32-ip" $outputdir
|
||||
set_property target_language VHDL [current_project]
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Add HDL source files
|
||||
# **************************************************************
|
||||
add_files [glob $neorv32_home/rtl/core/*.vhd]
|
||||
add_file $neorv32_home/rtl/core/mem/neorv32_dmem.default.vhd
|
||||
add_file $neorv32_home/rtl/core/mem/neorv32_imem.default.vhd
|
||||
add_file $neorv32_home/rtl/system_integration/$rtl_top
|
||||
|
||||
set_property library neorv32 [get_files [glob $neorv32_home/rtl/core/*.vhd]]
|
||||
set_property library neorv32 [get_files [glob $neorv32_home/rtl/core/mem/neorv32_*mem.default.vhd]]
|
||||
set_property library neorv32 [get_files [glob $neorv32_home/rtl/system_integration/$rtl_top]]
|
||||
|
||||
set_property top $rtl_top [current_fileset]
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Package as IP block
|
||||
# **************************************************************
|
||||
ipx::package_project -root_dir $outputdir/packaged_ip -vendor NEORV32 -library user -taxonomy /UserIP -import_files -set_current true -force
|
||||
set_property company_url https://github.com/stnolting/neorv32 [ipx::current_core]
|
||||
set_property description "The NEORV32 RISC-V Processor" [ipx::current_core]
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Set configuration dependencies: Interfaces
|
||||
# **************************************************************
|
||||
set_property enablement_dependency {$axi4_stream_en = true} [ipx::get_ports s0_axis_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$axi4_stream_en = true} [ipx::get_ports s1_axis_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$on_chip_debugger_en = true} [ipx::get_ports jtag_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$xip_en = true} [ipx::get_ports xip_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_gpio_num > 0} [ipx::get_ports gpio* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_uart0_en = true} [ipx::get_ports uart0_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_uart1_en = true} [ipx::get_ports uart1_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_spi_en = true} [ipx::get_ports spi_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_sdi_en = true} [ipx::get_ports sdi_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_twi_en = true} [ipx::get_ports twi_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_onewire_en = true} [ipx::get_ports onewire_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_pwm_num_ch > 0} [ipx::get_ports pwm_o -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_cfs_en = true} [ipx::get_ports cfs_* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_neoled_en = true} [ipx::get_ports neoled_o -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_mtime_en = true} [ipx::get_ports mtime_time_o -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_gptmr_en = true} [ipx::get_ports gptmr_trig_i -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$xirq_num_ch > 0} [ipx::get_ports xirq_i -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {$io_mtime_en = false} [ipx::get_ports mtime_irq_i -of_objects [ipx::current_core]]
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# -Configuration GUI: General
|
||||
# **************************************************************
|
||||
set_property display_name {Clock frequency (Hz)} [ipgui::get_guiparamspec -name "CLOCK_FREQUENCY" -component [ipx::current_core]]
|
||||
set_property tooltip {Frequency of the clk signal in Hz} [ipgui::get_guiparamspec -name "CLOCK_FREQUENCY" -component [ipx::current_core]]
|
||||
set_property display_name {HART ID} [ipgui::get_guiparamspec -name "HART_ID" -component [ipx::current_core]]
|
||||
set_property tooltip {For mhartid CSR} [ipgui::get_guiparamspec -name "HART_ID" -component [ipx::current_core]]
|
||||
set_property display_name {JEDEC ID} [ipgui::get_guiparamspec -name "JEDEC_ID" -component [ipx::current_core]]
|
||||
set_property tooltip {For JTAG tap identification and mvendorid CSR} [ipgui::get_guiparamspec -name "JEDEC_ID" -component [ipx::current_core]]
|
||||
set_property display_name {On-Chip Debugger} [ipgui::get_guiparamspec -name "ON_CHIP_DEBUGGER_EN" -component [ipx::current_core]]
|
||||
set_property display_name {AXI4-Lite (XBUS) timeout} [ipgui::get_guiparamspec -name "XBUS_TIMEOUT" -component [ipx::current_core]]
|
||||
set_property tooltip {Max number of clock cycles before AXI access times out} [ipgui::get_guiparamspec -name "XBUS_TIMEOUT" -component [ipx::current_core]]
|
||||
set_property display_name {AXI4-Lite cache (XBUS)} [ipgui::get_guiparamspec -name "XBUS_CACHE_EN" -component [ipx::current_core]]
|
||||
set_property display_name {AXI4-Lite cache (XBUS) number of blocks} [ipgui::get_guiparamspec -name "XBUS_CACHE_NUM_BLOCKS" -component [ipx::current_core]]
|
||||
set_property display_name {AXI4-Lite cache (XBUS) block size} [ipgui::get_guiparamspec -name "XBUS_CACHE_BLOCK_SIZE" -component [ipx::current_core]]
|
||||
set_property tooltip {In bytes} [ipgui::get_guiparamspec -name "XBUS_CACHE_BLOCK_SIZE" -component [ipx::current_core]]
|
||||
set_property display_name {AXI4-Stream source and sink} [ipgui::get_guiparamspec -name "AXI4_STREAM_EN" -component [ipx::current_core]]
|
||||
set_property display_name {AXI4-Stream input FIFO depth} [ipgui::get_guiparamspec -name "IO_SLINK_RX_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {AXI4-Stream output FIFO depth} [ipgui::get_guiparamspec -name "IO_SLINK_TX_FIFO" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_group -name {General} -component [ipx::current_core] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]] -display_name {General}
|
||||
ipgui::move_group -component [ipx::current_core] -order 0 [ipgui::get_groupspec -name "General" -component [ipx::current_core]] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 0 [ipgui::get_guiparamspec -name "CLOCK_FREQUENCY" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 1 [ipgui::get_guiparamspec -name "HART_ID" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 2 [ipgui::get_guiparamspec -name "JEDEC_ID" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 3 [ipgui::get_guiparamspec -name "ON_CHIP_DEBUGGER_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 4 [ipgui::get_guiparamspec -name "XBUS_TIMEOUT" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 5 [ipgui::get_guiparamspec -name "XBUS_CACHE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 6 [ipgui::get_guiparamspec -name "XBUS_CACHE_NUM_BLOCKS" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 7 [ipgui::get_guiparamspec -name "XBUS_CACHE_BLOCK_SIZE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 8 [ipgui::get_guiparamspec -name "AXI4_STREAM_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 9 [ipgui::get_guiparamspec -name "IO_SLINK_RX_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 10 [ipgui::get_guiparamspec -name "IO_SLINK_TX_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "General" -component [ipx::current_core]]
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Configuration GUI: CPU
|
||||
# **************************************************************
|
||||
set_property display_name {RISC-V A ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_A" -component [ipx::current_core]]
|
||||
set_property tooltip {Atomic memory operations} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_A" -component [ipx::current_core]]
|
||||
set_property display_name {Reservation set minimal granularity} [ipgui::get_guiparamspec -name "AMO_RVS_GRANULARITY" -component [ipx::current_core]]
|
||||
set_property tooltip {In bytes} [ipgui::get_guiparamspec -name "AMO_RVS_GRANULARITY" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V B ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_B" -component [ipx::current_core]]
|
||||
set_property tooltip {Bit-manipulation operations} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_B" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V C ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_C" -component [ipx::current_core]]
|
||||
set_property tooltip {Compressed instructions} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_C" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V E ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_E" -component [ipx::current_core]]
|
||||
set_property tooltip {Reduced register file size (16 entries)} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_E" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V M ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_M" -component [ipx::current_core]]
|
||||
set_property tooltip {Integer multiplication and division hardware} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_M" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V U ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_U" -component [ipx::current_core]]
|
||||
set_property tooltip {Less-privileged user-mode} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_U" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V Zfinx ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zfinx" -component [ipx::current_core]]
|
||||
set_property tooltip {Embedded FPU} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zfinx" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V Zihpm ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zihpm" -component [ipx::current_core]]
|
||||
set_property tooltip {Hardware performance monitors (HPMs)} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zihpm" -component [ipx::current_core]]
|
||||
set_property display_name {HPM counters} [ipgui::get_guiparamspec -name "HPM_NUM_CNTS" -component [ipx::current_core]]
|
||||
set_property tooltip {Numer of total hardware performance monitor counters} [ipgui::get_guiparamspec -name "HPM_NUM_CNTS" -component [ipx::current_core]]
|
||||
set_property display_name {HPM width} [ipgui::get_guiparamspec -name "HPM_CNT_WIDTH" -component [ipx::current_core]]
|
||||
set_property tooltip {Counter width in bits} [ipgui::get_guiparamspec -name "HPM_CNT_WIDTH" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V Zicntr ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zicntr" -component [ipx::current_core]]
|
||||
set_property tooltip {Base counters (cycles and instructions)} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zicntr" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V Zicond ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zicond" -component [ipx::current_core]]
|
||||
set_property tooltip {Conditional move instructions} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zicond" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V Zmmul ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zmmul" -component [ipx::current_core]]
|
||||
set_property tooltip {Integer multiplication-only hardware} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zmmul" -component [ipx::current_core]]
|
||||
set_property display_name {RISC-V Zxcfu ISA extension} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zxcfu" -component [ipx::current_core]]
|
||||
set_property tooltip {Custom-instructions unit} [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zxcfu" -component [ipx::current_core]]
|
||||
set_property display_name {DSP multiplier} [ipgui::get_guiparamspec -name "FAST_MUL_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Barrel shifter} [ipgui::get_guiparamspec -name "FAST_SHIFT_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Barrel shifter} [ipgui::get_guiparamspec -name "REGFILE_HW_RST" -component [ipx::current_core]]
|
||||
set_property display_name {PMP regions} [ipgui::get_guiparamspec -name "PMP_NUM_REGIONS" -component [ipx::current_core]]
|
||||
set_property tooltip {Numer of total physical memory protection regions} [ipgui::get_guiparamspec -name "PMP_NUM_REGIONS" -component [ipx::current_core]]
|
||||
set_property display_name {PMP minimal granularity} [ipgui::get_guiparamspec -name "PMP_MIN_GRANULARITY" -component [ipx::current_core]]
|
||||
set_property tooltip {In bytes} [ipgui::get_guiparamspec -name "PMP_MIN_GRANULARITY" -component [ipx::current_core]]
|
||||
set_property display_name {PMP TOR-mode enable} [ipgui::get_guiparamspec -name "PMP_TOR_MODE_EN" -component [ipx::current_core]]
|
||||
set_property tooltip {Top-of-region} [ipgui::get_guiparamspec -name "PMP_TOR_MODE_EN" -component [ipx::current_core]]
|
||||
set_property display_name {PMP NAP-mode enable} [ipgui::get_guiparamspec -name "PMP_NAP_MODE_EN" -component [ipx::current_core]]
|
||||
set_property tooltip {Naturally-aligned-power-of-two} [ipgui::get_guiparamspec -name "PMP_NAP_MODE_EN" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_group -name {CPU Configuration} -component [ipx::current_core] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]] -display_name {CPU Configuration}
|
||||
ipgui::move_group -component [ipx::current_core] -order 1 [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 0 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_A" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 1 [ipgui::get_guiparamspec -name "AMO_RVS_GRANULARITY" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 2 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_B" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 3 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_C" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 4 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_E" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 5 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_M" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 6 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_U" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 7 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zfinx" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 8 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zihpm" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 9 [ipgui::get_guiparamspec -name "HPM_NUM_CNTS" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 10 [ipgui::get_guiparamspec -name "HPM_CNT_WIDTH" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 11 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zicntr" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 12 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zicond" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 13 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zmmul" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 14 [ipgui::get_guiparamspec -name "CPU_EXTENSION_RISCV_Zxcfu" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 15 [ipgui::get_guiparamspec -name "FAST_MUL_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 16 [ipgui::get_guiparamspec -name "FAST_SHIFT_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 17 [ipgui::get_guiparamspec -name "REGFILE_HW_RST" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 18 [ipgui::get_guiparamspec -name "PMP_NUM_REGIONS" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 19 [ipgui::get_guiparamspec -name "PMP_MIN_GRANULARITY" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 20 [ipgui::get_guiparamspec -name "PMP_TOR_MODE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 21 [ipgui::get_guiparamspec -name "PMP_NAP_MODE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]]
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Configuration GUI: Memory System
|
||||
# **************************************************************
|
||||
set_property display_name {Internal instruction memory (IMEM)} [ipgui::get_guiparamspec -name "MEM_INT_IMEM_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Internal instruction memory size} [ipgui::get_guiparamspec -name "MEM_INT_IMEM_SIZE" -component [ipx::current_core]]
|
||||
set_property tooltip {In bytes} [ipgui::get_guiparamspec -name "MEM_INT_IMEM_SIZE" -component [ipx::current_core]]
|
||||
set_property display_name {Internal data memory (DMEM)} [ipgui::get_guiparamspec -name "MEM_INT_DMEM_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Internal data memory size} [ipgui::get_guiparamspec -name "MEM_INT_DMEM_SIZE" -component [ipx::current_core]]
|
||||
set_property tooltip {In bytes} [ipgui::get_guiparamspec -name "MEM_INT_DMEM_SIZE" -component [ipx::current_core]]
|
||||
set_property display_name {CPU instruction cache (ICACHE)} [ipgui::get_guiparamspec -name "ICACHE_EN" -component [ipx::current_core]]
|
||||
set_property display_name {CPU instruction cache (ICACHE) number of blocks} [ipgui::get_guiparamspec -name "ICACHE_NUM_BLOCKS" -component [ipx::current_core]]
|
||||
set_property display_name {CPU instruction cache (ICACHE) block size} [ipgui::get_guiparamspec -name "ICACHE_BLOCK_SIZE" -component [ipx::current_core]]
|
||||
set_property tooltip {In bytes} [ipgui::get_guiparamspec -name "ICACHE_BLOCK_SIZE" -component [ipx::current_core]]
|
||||
set_property display_name {CPU data cache (DCACHE)} [ipgui::get_guiparamspec -name "DCACHE_EN" -component [ipx::current_core]]
|
||||
set_property display_name {CPU data cache (DCACHE) number of blocks} [ipgui::get_guiparamspec -name "DCACHE_NUM_BLOCKS" -component [ipx::current_core]]
|
||||
set_property display_name {CPU data cache (DCACHE) block size} [ipgui::get_guiparamspec -name "DCACHE_BLOCK_SIZE" -component [ipx::current_core]]
|
||||
set_property tooltip {In bytes} [ipgui::get_guiparamspec -name "DCACHE_BLOCK_SIZE" -component [ipx::current_core]]
|
||||
set_property display_name {Execute in-place module (XIP)} [ipgui::get_guiparamspec -name "XIP_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Execute in-place module (XIP) cache} [ipgui::get_guiparamspec -name "XIP_CACHE_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Execute in-place module (XIP) cache number of blocks} [ipgui::get_guiparamspec -name "XIP_CACHE_NUM_BLOCKS" -component [ipx::current_core]]
|
||||
set_property display_name {Execute in-place module (XIP) cache block size} [ipgui::get_guiparamspec -name "XIP_CACHE_BLOCK_SIZE" -component [ipx::current_core]]
|
||||
set_property tooltip {In bytes} [ipgui::get_guiparamspec -name "XIP_CACHE_BLOCK_SIZE" -component [ipx::current_core]]
|
||||
set_property display_name {Internal bootloader} [ipgui::get_guiparamspec -name "INT_BOOTLOADER_EN" -component [ipx::current_core]]
|
||||
set_property tooltip {Start UART bootloader after reset} [ipgui::get_guiparamspec -name "INT_BOOTLOADER_EN" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_group -name {Memory System} -component [ipx::current_core] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]] -display_name {Memory System}
|
||||
ipgui::move_group -component [ipx::current_core] -order 2 [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 0 [ipgui::get_guiparamspec -name "MEM_INT_IMEM_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 1 [ipgui::get_guiparamspec -name "MEM_INT_IMEM_SIZE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 2 [ipgui::get_guiparamspec -name "MEM_INT_DMEM_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 3 [ipgui::get_guiparamspec -name "MEM_INT_DMEM_SIZE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 4 [ipgui::get_guiparamspec -name "ICACHE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 5 [ipgui::get_guiparamspec -name "ICACHE_NUM_BLOCKS" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 6 [ipgui::get_guiparamspec -name "ICACHE_BLOCK_SIZE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 7 [ipgui::get_guiparamspec -name "DCACHE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 8 [ipgui::get_guiparamspec -name "DCACHE_NUM_BLOCKS" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 9 [ipgui::get_guiparamspec -name "DCACHE_BLOCK_SIZE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 10 [ipgui::get_guiparamspec -name "XIP_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 11 [ipgui::get_guiparamspec -name "XIP_CACHE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 12 [ipgui::get_guiparamspec -name "XIP_CACHE_NUM_BLOCKS" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 13 [ipgui::get_guiparamspec -name "XIP_CACHE_BLOCK_SIZE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 14 [ipgui::get_guiparamspec -name "INT_BOOTLOADER_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Memory System" -component [ipx::current_core]]
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Configuration GUI: Peripherals
|
||||
# **************************************************************
|
||||
set_property display_name {External interrupt controller (XIRQ)} [ipgui::get_guiparamspec -name "XIRQ_NUM_CH" -component [ipx::current_core]]
|
||||
set_property display_name {External interrupt controller (XIRQ trigger type} [ipgui::get_guiparamspec -name "XIRQ_TRIGGER_TYPE" -component [ipx::current_core]]
|
||||
set_property tooltip {0=level, 1=edge} [ipgui::get_guiparamspec -name "XIRQ_TRIGGER_TYPE" -component [ipx::current_core]]
|
||||
set_property display_name {External interrupt controller (XIRQ trigger polarity} [ipgui::get_guiparamspec -name "XIRQ_TRIGGER_POLARITY" -component [ipx::current_core]]
|
||||
set_property tooltip {0=low-level/falling-edge, 1=high-level/rising-edge} [ipgui::get_guiparamspec -name "XIRQ_TRIGGER_POLARITY" -component [ipx::current_core]]
|
||||
set_property display_name {GPIO port pins} [ipgui::get_guiparamspec -name "IO_GPIO_NUM" -component [ipx::current_core]]
|
||||
set_property display_name {Machine timer} [ipgui::get_guiparamspec -name "IO_MTIME_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Primary UART (UART0)} [ipgui::get_guiparamspec -name "IO_UART0_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Primary UART (UART0) RX FIFO depth} [ipgui::get_guiparamspec -name "IO_UART0_RX_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {Primary UART (UART0) TX FIFO depth} [ipgui::get_guiparamspec -name "IO_UART0_TX_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {Secondary UART (UART1)} [ipgui::get_guiparamspec -name "IO_UART1_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Secondary UART (UART1) RX FIFO depth} [ipgui::get_guiparamspec -name "IO_UART1_RX_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {Secondary UART (UART1) TX FIFO depth} [ipgui::get_guiparamspec -name "IO_UART1_TX_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {SPI} [ipgui::get_guiparamspec -name "IO_SPI_EN" -component [ipx::current_core]]
|
||||
set_property display_name {SPI FIFO depth} [ipgui::get_guiparamspec -name "IO_SPI_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {SDI} [ipgui::get_guiparamspec -name "IO_SDI_EN" -component [ipx::current_core]]
|
||||
set_property display_name {SDI FIFO depth} [ipgui::get_guiparamspec -name "IO_SDI_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {TWI} [ipgui::get_guiparamspec -name "IO_TWI_EN" -component [ipx::current_core]]
|
||||
set_property display_name {TWI FIFO depth} [ipgui::get_guiparamspec -name "IO_TWI_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {PWM channels} [ipgui::get_guiparamspec -name "IO_PWM_NUM_CH" -component [ipx::current_core]]
|
||||
set_property display_name {Watchdog} [ipgui::get_guiparamspec -name "IO_WDT_EN" -component [ipx::current_core]]
|
||||
set_property display_name {TRNG} [ipgui::get_guiparamspec -name "IO_TRNG_EN" -component [ipx::current_core]]
|
||||
set_property display_name {TRNG FIFO depth} [ipgui::get_guiparamspec -name "IO_TRNG_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {Custom Functions Subsystem (CFU)} [ipgui::get_guiparamspec -name "IO_CFS_EN" -component [ipx::current_core]]
|
||||
set_property display_name {Custom Functions Subsystem (CFU) configuration string} [ipgui::get_guiparamspec -name "IO_CFS_CONFIG" -component [ipx::current_core]]
|
||||
set_property display_name {Custom Functions Subsystem (CFU) input port width} [ipgui::get_guiparamspec -name "IO_CFS_IN_SIZE" -component [ipx::current_core]]
|
||||
set_property display_name {Custom Functions Subsystem (CFU) output port width} [ipgui::get_guiparamspec -name "IO_CFS_OUT_SIZE" -component [ipx::current_core]]
|
||||
set_property display_name {NEOLED} [ipgui::get_guiparamspec -name "IO_NEOLED_EN" -component [ipx::current_core]]
|
||||
set_property display_name {NEOLED FIFO depth} [ipgui::get_guiparamspec -name "IO_NEOLED_TX_FIFO" -component [ipx::current_core]]
|
||||
set_property display_name {General Purpose Timer (GPTM)} [ipgui::get_guiparamspec -name "IO_GPTMR_EN" -component [ipx::current_core]]
|
||||
set_property display_name {ONEWIRE} [ipgui::get_guiparamspec -name "IO_ONEWIRE_EN" -component [ipx::current_core]]
|
||||
set_property display_name {DMA controller} [ipgui::get_guiparamspec -name "IO_DMA_EN" -component [ipx::current_core]]
|
||||
set_property display_name {CRC Unit} [ipgui::get_guiparamspec -name "IO_CRC_EN" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_group -name {Peripherals} -component [ipx::current_core] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]] -display_name {Peripherals}
|
||||
ipgui::move_group -component [ipx::current_core] -order 3 [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 0 [ipgui::get_guiparamspec -name "IO_GPIO_NUM" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 1 [ipgui::get_guiparamspec -name "IO_MTIME_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 2 [ipgui::get_guiparamspec -name "IO_UART0_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 3 [ipgui::get_guiparamspec -name "IO_UART0_RX_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 4 [ipgui::get_guiparamspec -name "IO_UART0_TX_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 5 [ipgui::get_guiparamspec -name "IO_UART1_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 6 [ipgui::get_guiparamspec -name "IO_UART1_RX_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 7 [ipgui::get_guiparamspec -name "IO_UART1_TX_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 8 [ipgui::get_guiparamspec -name "IO_SPI_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 9 [ipgui::get_guiparamspec -name "IO_SPI_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 10 [ipgui::get_guiparamspec -name "IO_SDI_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 11 [ipgui::get_guiparamspec -name "IO_SDI_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 12 [ipgui::get_guiparamspec -name "IO_TWI_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 13 [ipgui::get_guiparamspec -name "IO_TWI_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 14 [ipgui::get_guiparamspec -name "IO_PWM_NUM_CH" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 15 [ipgui::get_guiparamspec -name "IO_WDT_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 16 [ipgui::get_guiparamspec -name "IO_TRNG_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 17 [ipgui::get_guiparamspec -name "IO_TRNG_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 18 [ipgui::get_guiparamspec -name "IO_CFS_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 19 [ipgui::get_guiparamspec -name "IO_CFS_CONFIG" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 20 [ipgui::get_guiparamspec -name "IO_CFS_IN_SIZE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 21 [ipgui::get_guiparamspec -name "IO_CFS_OUT_SIZE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 22 [ipgui::get_guiparamspec -name "IO_NEOLED_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 23 [ipgui::get_guiparamspec -name "IO_NEOLED_TX_FIFO" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 24 [ipgui::get_guiparamspec -name "IO_GPTMR_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 25 [ipgui::get_guiparamspec -name "IO_ONEWIRE_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 26 [ipgui::get_guiparamspec -name "IO_DMA_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 27 [ipgui::get_guiparamspec -name "XIRQ_NUM_CH" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 28 [ipgui::get_guiparamspec -name "XIRQ_TRIGGER_TYPE" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 29 [ipgui::get_guiparamspec -name "XIRQ_TRIGGER_POLARITY" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
ipgui::move_param -component [ipx::current_core] -order 30 [ipgui::get_guiparamspec -name "IO_CRC_EN" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "Peripherals" -component [ipx::current_core]]
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Configuration GUI: IP logo
|
||||
# **************************************************************
|
||||
ipx::add_file_group -type utility {} [ipx::current_core]
|
||||
ipx::add_file ../../$neorv32_home/$logo [ipx::get_file_groups xilinx_utilityxitfiles -of_objects [ipx::current_core]]
|
||||
set_property type image [ipx::get_files ../../$neorv32_home/$logo -of_objects [ipx::get_file_groups xilinx_utilityxitfiles -of_objects [ipx::current_core]]]
|
||||
set_property type LOGO [ipx::get_files ../../$neorv32_home/$logo -of_objects [ipx::get_file_groups xilinx_utilityxitfiles -of_objects [ipx::current_core]]]
|
||||
|
||||
ipx::add_file_group -type gui_icon {} [ipx::current_core]
|
||||
ipx::add_file ../../$neorv32_home/$logo [ipx::get_file_groups xilinx_coreguiicon -of_objects [ipx::current_core]]
|
||||
set_property type image [ipx::get_files ../../$neorv32_home/$logo -of_objects [ipx::get_file_groups xilinx_coreguiicon -of_objects [ipx::current_core]]]
|
||||
set_property type LOGO [ipx::get_files ../../$neorv32_home/$logo -of_objects [ipx::get_file_groups xilinx_coreguiicon -of_objects [ipx::current_core]]]
|
||||
|
||||
|
||||
# **************************************************************
|
||||
# Finalize and add to IP repository
|
||||
# **************************************************************
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
set cur_dir [ file normalize .]
|
||||
set_property ip_repo_paths $cur_dir/$outputdir/packaged_ip [current_project]
|
||||
update_ip_catalog
|
||||
|
||||
close_project
|
||||
535
rtl/system_integration/neorv32_vivado_ip.vhd
Normal file
535
rtl/system_integration/neorv32_vivado_ip.vhd
Normal file
|
|
@ -0,0 +1,535 @@
|
|||
-- ================================================================================ --
|
||||
-- NEORV32 - Processor Top Entity with AXI4-Lite & AXI4-Stream Compatible Interface --
|
||||
-- -------------------------------------------------------------------------------- --
|
||||
-- Dedicated for IP packaging/integration using AMD Vivado. --
|
||||
-- Use the provided TCL script to automatically package this as IP module: --
|
||||
-- Vivado TCL console: > source neorv32_vivado_ip.tcl --
|
||||
-- See the NEORV32 Datasheet and User Guide for more information. --
|
||||
-- -------------------------------------------------------------------------------- --
|
||||
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
|
||||
-- Copyright (c) NEORV32 contributors. --
|
||||
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
|
||||
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
|
||||
-- SPDX-License-Identifier: BSD-3-Clause --
|
||||
-- ================================================================================ --
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library neorv32;
|
||||
use neorv32.neorv32_package.all;
|
||||
|
||||
entity neorv32_vivado_ip is
|
||||
generic (
|
||||
-- ------------------------------------------------------------
|
||||
-- Configuration Generics
|
||||
-- ------------------------------------------------------------
|
||||
-- AXI-Stream Interfaces --
|
||||
AXI4_STREAM_EN : boolean := false;
|
||||
-- General --
|
||||
CLOCK_FREQUENCY : natural := 0;
|
||||
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000";
|
||||
JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000";
|
||||
INT_BOOTLOADER_EN : boolean := false;
|
||||
-- On-Chip Debugger (OCD) --
|
||||
ON_CHIP_DEBUGGER_EN : boolean := false;
|
||||
-- RISC-V CPU Extensions --
|
||||
CPU_EXTENSION_RISCV_A : boolean := false;
|
||||
CPU_EXTENSION_RISCV_B : boolean := false;
|
||||
CPU_EXTENSION_RISCV_C : boolean := false;
|
||||
CPU_EXTENSION_RISCV_E : boolean := false;
|
||||
CPU_EXTENSION_RISCV_M : boolean := false;
|
||||
CPU_EXTENSION_RISCV_U : boolean := false;
|
||||
CPU_EXTENSION_RISCV_Zfinx : boolean := false;
|
||||
CPU_EXTENSION_RISCV_Zicntr : boolean := false;
|
||||
CPU_EXTENSION_RISCV_Zicond : boolean := false;
|
||||
CPU_EXTENSION_RISCV_Zihpm : boolean := false;
|
||||
CPU_EXTENSION_RISCV_Zmmul : boolean := false;
|
||||
CPU_EXTENSION_RISCV_Zxcfu : boolean := false;
|
||||
-- Tuning Options --
|
||||
FAST_MUL_EN : boolean := false;
|
||||
FAST_SHIFT_EN : boolean := false;
|
||||
REGFILE_HW_RST : boolean := false;
|
||||
-- Physical Memory Protection (PMP) --
|
||||
PMP_NUM_REGIONS : natural range 0 to 16 := 0;
|
||||
PMP_MIN_GRANULARITY : natural := 4;
|
||||
PMP_TOR_MODE_EN : boolean := false;
|
||||
PMP_NAP_MODE_EN : boolean := false;
|
||||
-- Hardware Performance Monitors (HPM) --
|
||||
HPM_NUM_CNTS : natural range 0 to 13 := 0;
|
||||
HPM_CNT_WIDTH : natural range 0 to 64 := 40;
|
||||
-- Atomic Memory Access - Reservation Set Granularity --
|
||||
AMO_RVS_GRANULARITY : natural := 4;
|
||||
-- Internal Instruction memory --
|
||||
MEM_INT_IMEM_EN : boolean := false;
|
||||
MEM_INT_IMEM_SIZE : natural := 16*1024;
|
||||
-- Internal Data memory --
|
||||
MEM_INT_DMEM_EN : boolean := false;
|
||||
MEM_INT_DMEM_SIZE : natural := 8*1024;
|
||||
-- Internal Cache memory --
|
||||
ICACHE_EN : boolean := false;
|
||||
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
|
||||
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
|
||||
-- Internal Data Cache (dCACHE) --
|
||||
DCACHE_EN : boolean := false;
|
||||
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
|
||||
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
|
||||
-- External Bus Interface --
|
||||
XBUS_TIMEOUT : natural range 8 to 65536 := 64;
|
||||
XBUS_CACHE_EN : boolean := false;
|
||||
XBUS_CACHE_NUM_BLOCKS : natural range 1 to 256 := 8;
|
||||
XBUS_CACHE_BLOCK_SIZE : natural range 1 to 2**16 := 256;
|
||||
-- Execute in-place module (XIP) --
|
||||
XIP_EN : boolean := false;
|
||||
XIP_CACHE_EN : boolean := false;
|
||||
XIP_CACHE_NUM_BLOCKS : natural range 1 to 256 := 8;
|
||||
XIP_CACHE_BLOCK_SIZE : natural range 1 to 2**16 := 256;
|
||||
-- External Interrupts Controller (XIRQ) --
|
||||
XIRQ_NUM_CH : natural := 0;
|
||||
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff";
|
||||
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff";
|
||||
-- Processor peripherals --
|
||||
IO_GPIO_NUM : natural range 0 to 64 := 0;
|
||||
IO_MTIME_EN : boolean := false;
|
||||
IO_UART0_EN : boolean := false;
|
||||
IO_UART0_RX_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_UART0_TX_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_UART1_EN : boolean := false;
|
||||
IO_UART1_RX_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_UART1_TX_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_SPI_EN : boolean := false;
|
||||
IO_SPI_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_SDI_EN : boolean := false;
|
||||
IO_SDI_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_TWI_EN : boolean := false;
|
||||
IO_TWI_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_PWM_NUM_CH : natural range 0 to 12 := 0;
|
||||
IO_WDT_EN : boolean := false;
|
||||
IO_TRNG_EN : boolean := false;
|
||||
IO_TRNG_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_CFS_EN : boolean := false;
|
||||
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000";
|
||||
IO_CFS_IN_SIZE : natural := 32;
|
||||
IO_CFS_OUT_SIZE : natural := 32;
|
||||
IO_NEOLED_EN : boolean := false;
|
||||
IO_NEOLED_TX_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_GPTMR_EN : boolean := false;
|
||||
IO_ONEWIRE_EN : boolean := false;
|
||||
IO_DMA_EN : boolean := false;
|
||||
IO_SLINK_RX_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_SLINK_TX_FIFO : natural range 1 to 2**15 := 1;
|
||||
IO_CRC_EN : boolean := false
|
||||
);
|
||||
port (
|
||||
-- ------------------------------------------------------------
|
||||
-- Global Control
|
||||
-- ------------------------------------------------------------
|
||||
clk : in std_ulogic;
|
||||
resetn : in std_ulogic; -- low-active
|
||||
-- ------------------------------------------------------------
|
||||
-- AXI4-Lite-Compatible Host Interface (always available)
|
||||
-- ------------------------------------------------------------
|
||||
-- Clock and Reset --
|
||||
-- m_axi_aclk : in std_ulogic := '0'; -- just to satisfy Vivado, but not actually used!
|
||||
-- m_axi_aresetn : in std_ulogic := '0'; -- just to satisfy Vivado, but not actually used!
|
||||
-- Write Address Channel --
|
||||
m_axi_awaddr : out std_ulogic_vector(31 downto 0);
|
||||
m_axi_awprot : out std_ulogic_vector(2 downto 0);
|
||||
m_axi_awvalid : out std_ulogic;
|
||||
m_axi_awready : in std_ulogic := '0';
|
||||
-- Write Data Channel --
|
||||
m_axi_wdata : out std_ulogic_vector(31 downto 0);
|
||||
m_axi_wstrb : out std_ulogic_vector(3 downto 0);
|
||||
m_axi_wvalid : out std_ulogic;
|
||||
m_axi_wready : in std_ulogic := '0';
|
||||
-- Read Address Channel --
|
||||
m_axi_araddr : out std_ulogic_vector(31 downto 0);
|
||||
m_axi_arprot : out std_ulogic_vector(2 downto 0);
|
||||
m_axi_arvalid : out std_ulogic;
|
||||
m_axi_arready : in std_ulogic := '0';
|
||||
-- Read Data Channel --
|
||||
m_axi_rdata : in std_ulogic_vector(31 downto 0) := x"00000000";
|
||||
m_axi_rresp : in std_ulogic_vector(1 downto 0) := "00";
|
||||
m_axi_rvalid : in std_ulogic := '0';
|
||||
m_axi_rready : out std_ulogic;
|
||||
-- Write Response Channel --
|
||||
m_axi_bresp : in std_ulogic_vector(1 downto 0) := "00";
|
||||
m_axi_bvalid : in std_ulogic := '0';
|
||||
m_axi_bready : out std_ulogic;
|
||||
-- ------------------------------------------------------------
|
||||
-- AXI4-Stream-Compatible Interfaces (available if AXI4_STREAM_EN = true)
|
||||
-- ------------------------------------------------------------
|
||||
-- Source --
|
||||
-- s0_axis_aclk : in std_ulogic := '0'; -- just to satisfy Vivado, but not actually used!
|
||||
s0_axis_tvalid : out std_ulogic;
|
||||
s0_axis_tready : in std_ulogic := '0';
|
||||
s0_axis_tdata : out std_ulogic_vector(31 downto 0);
|
||||
s0_axis_tlast : out std_ulogic;
|
||||
-- Sink --
|
||||
-- s1_axis_aclk : in std_ulogic := '0'; -- just to satisfy Vivado, but not actually used!
|
||||
s1_axis_tvalid : in std_ulogic := '0';
|
||||
s1_axis_tready : out std_ulogic;
|
||||
s1_axis_tdata : in std_ulogic_vector(31 downto 0) := x"00000000";
|
||||
s1_axis_tlast : in std_ulogic := '0';
|
||||
-- ------------------------------------------------------------
|
||||
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true)
|
||||
-- ------------------------------------------------------------
|
||||
jtag_trst_i : in std_ulogic := '0';
|
||||
jtag_tck_i : in std_ulogic := '0';
|
||||
jtag_tdi_i : in std_ulogic := '0';
|
||||
jtag_tdo_o : out std_ulogic := '0';
|
||||
jtag_tms_i : in std_ulogic := '0';
|
||||
-- ------------------------------------------------------------
|
||||
-- Processor IO
|
||||
-- ------------------------------------------------------------
|
||||
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
|
||||
xip_csn_o : out std_ulogic;
|
||||
xip_clk_o : out std_ulogic;
|
||||
xip_dat_i : in std_ulogic := '0';
|
||||
xip_dat_o : out std_ulogic;
|
||||
-- GPIO (available if IO_GPIO_NUM > 0) --
|
||||
gpio_o : out std_ulogic_vector(63 downto 0);
|
||||
gpio_i : in std_ulogic_vector(63 downto 0) := x"0000000000000000";
|
||||
-- primary UART0 (available if IO_UART0_EN = true) --
|
||||
uart0_txd_o : out std_ulogic;
|
||||
uart0_rxd_i : in std_ulogic := '0';
|
||||
uart0_rts_o : out std_ulogic;
|
||||
uart0_cts_i : in std_ulogic := '0';
|
||||
-- secondary UART1 (available if IO_UART1_EN = true) --
|
||||
uart1_txd_o : out std_ulogic;
|
||||
uart1_rxd_i : in std_ulogic := '0';
|
||||
uart1_rts_o : out std_ulogic;
|
||||
uart1_cts_i : in std_ulogic := '0';
|
||||
-- SPI (available if IO_SPI_EN = true) --
|
||||
spi_clk_o : out std_ulogic;
|
||||
spi_dat_o : out std_ulogic;
|
||||
spi_dat_i : in std_ulogic := '0';
|
||||
spi_csn_o : out std_ulogic_vector(7 downto 0); -- SPI CS
|
||||
-- SDI (available if IO_SDI_EN = true) --
|
||||
sdi_clk_i : in std_ulogic := '0';
|
||||
sdi_dat_o : out std_ulogic;
|
||||
sdi_dat_i : in std_ulogic := '0';
|
||||
sdi_csn_i : in std_ulogic := '0';
|
||||
-- TWI (available if IO_TWI_EN = true) --
|
||||
twi_sda_i : in std_ulogic := '0';
|
||||
twi_sda_o : out std_ulogic;
|
||||
twi_scl_i : in std_ulogic := '0';
|
||||
twi_scl_o : out std_ulogic;
|
||||
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
|
||||
onewire_i : in std_ulogic := '0';
|
||||
onewire_o : out std_ulogic;
|
||||
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
||||
pwm_o : out std_ulogic_vector(11 downto 0);
|
||||
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
||||
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => '0');
|
||||
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0);
|
||||
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
||||
neoled_o : out std_ulogic;
|
||||
-- Machine timer system time (available if IO_MTIME_EN = true) --
|
||||
mtime_time_o : out std_ulogic_vector(63 downto 0);
|
||||
-- GPTMR timer capture (available if IO_GPTMR_EN = true) --
|
||||
gptmr_trig_i : in std_ulogic := '0';
|
||||
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
||||
xirq_i : in std_ulogic_vector(31 downto 0) := x"00000000";
|
||||
-- CPU Interrupts --
|
||||
mtime_irq_i : in std_ulogic := '0';
|
||||
msw_irq_i : in std_ulogic := '0';
|
||||
mext_irq_i : in std_ulogic := '0'
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_vivado_ip_rtl of neorv32_vivado_ip is
|
||||
|
||||
-- internal wishbone bus --
|
||||
type wb_bus_t is record
|
||||
adr : std_ulogic_vector(31 downto 0);
|
||||
di : std_ulogic_vector(31 downto 0);
|
||||
do : std_ulogic_vector(31 downto 0);
|
||||
we : std_ulogic;
|
||||
sel : std_ulogic_vector(03 downto 0);
|
||||
cyc : std_ulogic;
|
||||
ack : std_ulogic;
|
||||
err : std_ulogic;
|
||||
end record;
|
||||
signal wb_core : wb_bus_t;
|
||||
|
||||
-- AXI bridge control --
|
||||
type axi_ctrl_t is record
|
||||
radr_received, wadr_received, wdat_received : std_ulogic;
|
||||
end record;
|
||||
signal axi_ctrl : axi_ctrl_t;
|
||||
|
||||
begin
|
||||
|
||||
-- The Core Of The Problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_top_inst: neorv32_top
|
||||
generic map (
|
||||
-- General --
|
||||
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
|
||||
CLOCK_GATING_EN => false, -- clock gating is not supported here
|
||||
HART_ID => HART_ID,
|
||||
JEDEC_ID => JEDEC_ID,
|
||||
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN,
|
||||
-- On-Chip Debugger --
|
||||
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN,
|
||||
DM_LEGACY_MODE => false,
|
||||
-- RISC-V CPU Extensions --
|
||||
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A,
|
||||
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B,
|
||||
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C,
|
||||
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E,
|
||||
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M,
|
||||
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U,
|
||||
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx,
|
||||
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,
|
||||
CPU_EXTENSION_RISCV_Zicond => CPU_EXTENSION_RISCV_Zicond,
|
||||
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm,
|
||||
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul,
|
||||
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu,
|
||||
-- Extension Options --
|
||||
FAST_MUL_EN => FAST_MUL_EN,
|
||||
FAST_SHIFT_EN => FAST_SHIFT_EN,
|
||||
REGFILE_HW_RST => REGFILE_HW_RST,
|
||||
-- Physical Memory Protection --
|
||||
PMP_NUM_REGIONS => PMP_NUM_REGIONS,
|
||||
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY,
|
||||
PMP_TOR_MODE_EN => PMP_TOR_MODE_EN,
|
||||
PMP_NAP_MODE_EN => PMP_NAP_MODE_EN,
|
||||
-- Hardware Performance Monitors --
|
||||
HPM_NUM_CNTS => HPM_NUM_CNTS,
|
||||
HPM_CNT_WIDTH => HPM_CNT_WIDTH,
|
||||
-- Atomic Memory Access - Reservation Set Granularity --
|
||||
AMO_RVS_GRANULARITY => AMO_RVS_GRANULARITY,
|
||||
-- Internal Instruction memory --
|
||||
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN,
|
||||
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE,
|
||||
-- Internal Data memory --
|
||||
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN,
|
||||
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE,
|
||||
-- Internal Cache memory --
|
||||
ICACHE_EN => ICACHE_EN,
|
||||
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS,
|
||||
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE,
|
||||
-- Internal Data Cache (dCACHE) --
|
||||
DCACHE_EN => DCACHE_EN,
|
||||
DCACHE_NUM_BLOCKS => DCACHE_NUM_BLOCKS,
|
||||
DCACHE_BLOCK_SIZE => DCACHE_BLOCK_SIZE,
|
||||
-- External bus interface --
|
||||
XBUS_EN => true,
|
||||
XBUS_TIMEOUT => XBUS_TIMEOUT,
|
||||
XBUS_REGSTAGE_EN => false,
|
||||
XBUS_CACHE_EN => XBUS_CACHE_EN,
|
||||
XBUS_CACHE_NUM_BLOCKS => XBUS_CACHE_NUM_BLOCKS,
|
||||
XBUS_CACHE_BLOCK_SIZE => XBUS_CACHE_BLOCK_SIZE,
|
||||
-- Execute in-place module --
|
||||
XIP_EN => XIP_EN,
|
||||
XIP_CACHE_EN => XIP_CACHE_EN,
|
||||
XIP_CACHE_NUM_BLOCKS => XIP_CACHE_NUM_BLOCKS,
|
||||
XIP_CACHE_BLOCK_SIZE => XIP_CACHE_BLOCK_SIZE,
|
||||
-- External Interrupts Controller --
|
||||
XIRQ_NUM_CH => XIRQ_NUM_CH,
|
||||
XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE,
|
||||
XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY,
|
||||
-- Processor peripherals --
|
||||
IO_GPIO_NUM => IO_GPIO_NUM,
|
||||
IO_MTIME_EN => IO_MTIME_EN,
|
||||
IO_UART0_EN => IO_UART0_EN,
|
||||
IO_UART0_RX_FIFO => IO_UART0_RX_FIFO,
|
||||
IO_UART0_TX_FIFO => IO_UART0_TX_FIFO,
|
||||
IO_UART1_EN => IO_UART1_EN,
|
||||
IO_UART1_RX_FIFO => IO_UART1_RX_FIFO,
|
||||
IO_UART1_TX_FIFO => IO_UART1_TX_FIFO,
|
||||
IO_SPI_EN => IO_SPI_EN,
|
||||
IO_SPI_FIFO => IO_SPI_FIFO,
|
||||
IO_SDI_EN => IO_SDI_EN,
|
||||
IO_SDI_FIFO => IO_SDI_FIFO,
|
||||
IO_TWI_EN => IO_TWI_EN,
|
||||
IO_TWI_FIFO => IO_TWI_FIFO,
|
||||
IO_PWM_NUM_CH => IO_PWM_NUM_CH,
|
||||
IO_WDT_EN => IO_WDT_EN,
|
||||
IO_TRNG_EN => IO_TRNG_EN,
|
||||
IO_TRNG_FIFO => IO_TRNG_FIFO,
|
||||
IO_CFS_EN => IO_CFS_EN,
|
||||
IO_CFS_CONFIG => IO_CFS_CONFIG,
|
||||
IO_CFS_IN_SIZE => IO_CFS_IN_SIZE,
|
||||
IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE,
|
||||
IO_NEOLED_EN => IO_NEOLED_EN,
|
||||
IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO,
|
||||
IO_GPTMR_EN => IO_GPTMR_EN,
|
||||
IO_ONEWIRE_EN => IO_ONEWIRE_EN,
|
||||
IO_DMA_EN => IO_DMA_EN,
|
||||
IO_SLINK_EN => AXI4_STREAM_EN,
|
||||
IO_SLINK_RX_FIFO => IO_SLINK_RX_FIFO,
|
||||
IO_SLINK_TX_FIFO => IO_SLINK_TX_FIFO,
|
||||
IO_CRC_EN => IO_CRC_EN
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => clk,
|
||||
rstn_i => resetn,
|
||||
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
|
||||
jtag_trst_i => jtag_trst_i,
|
||||
jtag_tck_i => jtag_tck_i,
|
||||
jtag_tdi_i => jtag_tdi_i,
|
||||
jtag_tdo_o => jtag_tdo_o,
|
||||
jtag_tms_i => jtag_tms_i,
|
||||
-- External bus interface (available if XBUS_EN = true) --
|
||||
xbus_adr_o => wb_core.adr,
|
||||
xbus_dat_i => wb_core.di,
|
||||
xbus_dat_o => wb_core.do,
|
||||
xbus_we_o => wb_core.we,
|
||||
xbus_sel_o => wb_core.sel,
|
||||
xbus_stb_o => open,
|
||||
xbus_cyc_o => wb_core.cyc,
|
||||
xbus_ack_i => wb_core.ack,
|
||||
xbus_err_i => wb_core.err,
|
||||
-- Stream Link Interface (available if IO_SLINK_EN = true) --
|
||||
slink_rx_dat_i => s1_axis_tdata,
|
||||
slink_rx_val_i => s1_axis_tvalid,
|
||||
slink_rx_lst_i => s1_axis_tlast,
|
||||
slink_rx_rdy_o => s1_axis_tready,
|
||||
slink_tx_dat_o => s0_axis_tdata,
|
||||
slink_tx_val_o => s0_axis_tvalid,
|
||||
slink_tx_lst_o => s0_axis_tlast,
|
||||
slink_tx_rdy_i => s0_axis_tready,
|
||||
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
|
||||
xip_csn_o => xip_csn_o,
|
||||
xip_clk_o => xip_clk_o,
|
||||
xip_dat_i => xip_dat_i,
|
||||
xip_dat_o => xip_dat_o,
|
||||
-- GPIO (available if IO_GPIO_NUM > 0) --
|
||||
gpio_o => gpio_o,
|
||||
gpio_i => gpio_i,
|
||||
-- primary UART0 (available if IO_UART0_EN = true) --
|
||||
uart0_txd_o => uart0_txd_o,
|
||||
uart0_rxd_i => uart0_rxd_i,
|
||||
uart0_rts_o => uart0_rts_o,
|
||||
uart0_cts_i => uart0_cts_i,
|
||||
-- secondary UART1 (available if IO_UART1_EN = true) --
|
||||
uart1_txd_o => uart1_txd_o,
|
||||
uart1_rxd_i => uart1_rxd_i,
|
||||
uart1_rts_o => uart1_rts_o,
|
||||
uart1_cts_i => uart1_cts_i,
|
||||
-- SPI (available if IO_SPI_EN = true) --
|
||||
spi_clk_o => spi_clk_o,
|
||||
spi_dat_o => spi_dat_o,
|
||||
spi_dat_i => spi_dat_i,
|
||||
spi_csn_o => spi_csn_o,
|
||||
-- TWI (available if IO_TWI_EN = true) --
|
||||
twi_sda_i => twi_sda_i,
|
||||
twi_sda_o => twi_sda_o,
|
||||
twi_scl_i => twi_scl_i,
|
||||
twi_scl_o => twi_scl_o,
|
||||
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
|
||||
onewire_i => onewire_i,
|
||||
onewire_o => onewire_o,
|
||||
-- PWM available if IO_PWM_NUM_CH > 0) --
|
||||
pwm_o => pwm_o,
|
||||
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
||||
cfs_in_i => cfs_in_i,
|
||||
cfs_out_o => cfs_out_o,
|
||||
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
||||
neoled_o => neoled_o,
|
||||
-- Machine timer system time (available if IO_MTIME_EN = true) --
|
||||
mtime_time_o => mtime_time_o,
|
||||
-- GPTMR timer capture (available if IO_GPTMR_EN = true) --
|
||||
gptmr_trig_i => gptmr_trig_i,
|
||||
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
||||
xirq_i => xirq_i,
|
||||
-- CPU Interrupts --
|
||||
mtime_irq_i => mtime_irq_i,
|
||||
msw_irq_i => msw_irq_i,
|
||||
mext_irq_i => mext_irq_i
|
||||
);
|
||||
|
||||
|
||||
-- Wishbone to AXI4-Lite Bridge -----------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
axi_arbiter: process(resetn, clk)
|
||||
begin
|
||||
if (resetn = '0') then
|
||||
axi_ctrl.radr_received <= '0';
|
||||
axi_ctrl.wadr_received <= '0';
|
||||
axi_ctrl.wdat_received <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if (wb_core.cyc = '0') then -- idle
|
||||
axi_ctrl.radr_received <= '0';
|
||||
axi_ctrl.wadr_received <= '0';
|
||||
axi_ctrl.wdat_received <= '0';
|
||||
else -- busy
|
||||
-- "read address received" flag --
|
||||
if (wb_core.we = '0') then -- pending READ
|
||||
if (m_axi_arready = '1') then -- read address received by interconnect?
|
||||
axi_ctrl.radr_received <= '1';
|
||||
end if;
|
||||
end if;
|
||||
-- "write address received" flag --
|
||||
if (wb_core.we = '1') then -- pending WRITE
|
||||
if (m_axi_awready = '1') then -- write address received by interconnect?
|
||||
axi_ctrl.wadr_received <= '1';
|
||||
end if;
|
||||
end if;
|
||||
-- "write data received" flag --
|
||||
if (wb_core.we = '1') then -- pending WRITE
|
||||
if (m_axi_wready = '1') then -- write data received by interconnect?
|
||||
axi_ctrl.wdat_received <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process axi_arbiter;
|
||||
|
||||
|
||||
-- read address channel --
|
||||
m_axi_araddr <= wb_core.adr;
|
||||
m_axi_arvalid <= wb_core.cyc and (not wb_core.we) and (not axi_ctrl.radr_received);
|
||||
m_axi_arprot <= "000";
|
||||
|
||||
-- read data channel --
|
||||
m_axi_rready <= wb_core.cyc and (not wb_core.we);
|
||||
wb_core.di <= m_axi_rdata;
|
||||
|
||||
-- write address channel --
|
||||
m_axi_awaddr <= wb_core.adr;
|
||||
m_axi_awvalid <= wb_core.cyc and wb_core.we and (not axi_ctrl.wadr_received);
|
||||
m_axi_awprot <= "000";
|
||||
|
||||
-- write data channel --
|
||||
m_axi_wdata <= wb_core.do;
|
||||
m_axi_wvalid <= wb_core.cyc and wb_core.we and (not axi_ctrl.wdat_received);
|
||||
m_axi_wstrb <= wb_core.sel;
|
||||
|
||||
-- write response channel --
|
||||
m_axi_bready <= wb_core.cyc and wb_core.we;
|
||||
|
||||
|
||||
-- read/write response --
|
||||
axi_response: process(wb_core, m_axi_bvalid, m_axi_bresp, m_axi_rvalid, m_axi_rresp)
|
||||
begin
|
||||
wb_core.ack <= '0'; -- default
|
||||
wb_core.err <= '0'; -- default
|
||||
if (wb_core.cyc = '1') then -- bus operation in progress
|
||||
if (wb_core.we = '1') then -- write operation
|
||||
if (m_axi_bvalid = '1') then -- valid response
|
||||
if (m_axi_bresp = "00") then -- status check
|
||||
wb_core.ack <= '1'; -- OK
|
||||
else
|
||||
wb_core.err <= '1'; -- ERROR!
|
||||
end if;
|
||||
end if;
|
||||
else -- read operation
|
||||
if (m_axi_rvalid = '1') then -- valid response
|
||||
if (m_axi_rresp = "00") then -- status check
|
||||
wb_core.ack <= '1'; -- OK
|
||||
else
|
||||
wb_core.err <= '1'; -- ERROR!
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process axi_response;
|
||||
|
||||
|
||||
end architecture neorv32_vivado_ip_rtl;
|
||||
Loading…
Add table
Add a link
Reference in a new issue