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Merge pull request #64 from umarcor/sim-uart
[sim] split UART logging component, make self-checking
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stnolting
GitHub
commit
a795497fb1
2 changed files with 108 additions and 110 deletions
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@ -94,20 +94,10 @@ architecture neorv32_tb_rtl of neorv32_tb is
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-- simulation uart0 receiver --
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signal uart0_txd : std_ulogic; -- local loop-back
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signal uart0_cts : std_ulogic; -- local loop-back
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signal uart0_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart0_rx_busy : std_ulogic := '0';
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signal uart0_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart0_rx_baud_cnt : real;
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signal uart0_rx_bitcnt : natural;
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-- simulation uart1 receiver --
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signal uart1_txd : std_ulogic; -- local loop-back
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signal uart1_cts : std_ulogic; -- local loop-back
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signal uart1_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart1_rx_busy : std_ulogic := '0';
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signal uart1_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart1_rx_baud_cnt : real;
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signal uart1_rx_bitcnt : natural;
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-- gpio --
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signal gpio : std_ulogic_vector(31 downto 0);
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@ -177,6 +167,7 @@ architecture neorv32_tb_rtl of neorv32_tb is
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begin
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-- Clock/Reset Generator ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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clk_gen <= not clk_gen after (t_clock_c/2);
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@ -316,109 +307,27 @@ begin
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twi_scl <= 'H';
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twi_sda <= 'H';
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-- Console UART0 Receiver -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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uart0_rx_console: process(clk_gen)
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variable i : integer;
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variable l : line;
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uart_checkers : block is
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begin
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-- "UART" --
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if rising_edge(clk_gen) then
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-- synchronizer --
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uart0_rx_sync <= uart0_rx_sync(3 downto 0) & uart0_txd;
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-- arbiter --
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if (uart0_rx_busy = '0') then -- idle
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uart0_rx_busy <= '0';
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uart0_rx_baud_cnt <= round(0.5 * uart0_baud_val_c);
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uart0_rx_bitcnt <= 9;
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if (uart0_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
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uart0_rx_busy <= '1';
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end if;
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else
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if (uart0_rx_baud_cnt <= 0.0) then
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if (uart0_rx_bitcnt = 1) then
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uart0_rx_baud_cnt <= round(0.5 * uart0_baud_val_c);
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else
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uart0_rx_baud_cnt <= round(uart0_baud_val_c);
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end if;
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if (uart0_rx_bitcnt = 0) then
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uart0_rx_busy <= '0'; -- done
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i := to_integer(unsigned(uart0_rx_sreg(8 downto 1)));
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if (i < 32) or (i > 32+95) then -- printable char?
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report "NEORV32_TB_UART0.TX: (" & integer'image(i) & ")"; -- print code
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else
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report "NEORV32_TB_UART0.TX: " & character'val(i); -- print ASCII
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end if;
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if (i = 10) then -- Linux line break
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writeline(file_uart0_tx_out, l);
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elsif (i /= 13) then -- Remove additional carriage return
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write(l, character'val(i));
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end if;
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else
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uart0_rx_sreg <= uart0_rx_sync(4) & uart0_rx_sreg(8 downto 1);
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uart0_rx_bitcnt <= uart0_rx_bitcnt - 1;
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end if;
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else
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uart0_rx_baud_cnt <= uart0_rx_baud_cnt - 1.0;
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end if;
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end if;
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end if;
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end process uart0_rx_console;
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uart0_checker: entity work.uart_rx
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generic map (
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name => "uart0",
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expected => nul & nul & cr & lf & "<< PROCESSOR CHECK >>" & cr & lf & "build: ",
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uart_baud_val_c => uart0_baud_val_c)
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port map (
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clk => clk_gen,
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uart_txd => uart0_txd);
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-- Console UART1 Receiver -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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uart1_rx_console: process(clk_gen)
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variable i : integer;
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variable l : line;
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begin
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-- "UART" --
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if rising_edge(clk_gen) then
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-- synchronizer --
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uart1_rx_sync <= uart1_rx_sync(3 downto 0) & uart1_txd;
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-- arbiter --
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if (uart1_rx_busy = '0') then -- idle
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uart1_rx_busy <= '0';
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uart1_rx_baud_cnt <= round(0.5 * uart1_baud_val_c);
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uart1_rx_bitcnt <= 9;
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if (uart1_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
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uart1_rx_busy <= '1';
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end if;
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else
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if (uart1_rx_baud_cnt <= 0.0) then
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if (uart1_rx_bitcnt = 1) then
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uart1_rx_baud_cnt <= round(0.5 * uart1_baud_val_c);
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else
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uart1_rx_baud_cnt <= round(uart1_baud_val_c);
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end if;
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if (uart1_rx_bitcnt = 0) then
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uart1_rx_busy <= '0'; -- done
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i := to_integer(unsigned(uart1_rx_sreg(8 downto 1)));
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if (i < 32) or (i > 32+95) then -- printable char?
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report "NEORV32_TB_UART1.TX: (" & integer'image(i) & ")"; -- print code
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else
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report "NEORV32_TB_UART1.TX: " & character'val(i); -- print ASCII
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end if;
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if (i = 10) then -- Linux line break
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writeline(file_uart1_tx_out, l);
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elsif (i /= 13) then -- Remove additional carriage return
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write(l, character'val(i));
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end if;
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else
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uart1_rx_sreg <= uart1_rx_sync(4) & uart1_rx_sreg(8 downto 1);
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uart1_rx_bitcnt <= uart1_rx_bitcnt - 1;
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end if;
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else
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uart1_rx_baud_cnt <= uart1_rx_baud_cnt - 1.0;
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end if;
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end if;
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end if;
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end process uart1_rx_console;
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uart1_checker: entity work.uart_rx
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generic map (
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name => "uart1",
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expected => nul & nul & etx,
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uart_baud_val_c => uart1_baud_val_c)
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port map (
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clk => clk_gen,
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uart_txd => uart1_txd);
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end block;
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-- Wishbone Fabric ------------------------------------------------------------------------
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89
sim/uart_rx.vhd
Normal file
89
sim/uart_rx.vhd
Normal file
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@ -0,0 +1,89 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use std.textio.all;
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entity uart_rx is
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generic (
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name : string;
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expected : string;
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uart_baud_val_c : real);
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port (
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clk : in std_ulogic;
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uart_txd : in std_ulogic
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);
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end entity;
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architecture a of uart_rx is
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signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart_rx_busy : std_ulogic := '0';
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signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart_rx_baud_cnt : real;
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signal uart_rx_bitcnt : natural;
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_" & name & ".out";
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begin
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uart_rx_console : process(clk)
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variable i : integer;
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variable l : line;
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variable expected_idx : positive := 1;
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begin
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-- "UART" --
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if rising_edge(clk) then
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-- synchronizer --
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uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
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-- arbiter --
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if (uart_rx_busy = '0') then -- idle
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uart_rx_busy <= '0';
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uart_rx_baud_cnt <= round(0.5 * uart_baud_val_c);
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uart_rx_bitcnt <= 9;
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if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
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uart_rx_busy <= '1';
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end if;
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else
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if (uart_rx_baud_cnt <= 0.0) then
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if (uart_rx_bitcnt = 1) then
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uart_rx_baud_cnt <= round(0.5 * uart_baud_val_c);
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else
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uart_rx_baud_cnt <= round(uart_baud_val_c);
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end if;
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if (uart_rx_bitcnt = 0) then
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uart_rx_busy <= '0'; -- done
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i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
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if (expected_idx < expected'length) or
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((expected_idx = expected'length) and (expected(expected'length) /= etx)) then
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assert character'val(i) = expected(expected_idx)
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report "Got " & character'val(i) & ", expected " & expected(expected_idx);
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else
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assert expected(expected'length) /= etx report "Extra characters received";
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end if;
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expected_idx := expected_idx + 1;
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if (i < 32) or (i > 32+95) then -- printable char?
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report name & ".tx: (" & integer'image(i) & ")"; -- print code
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else
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report name & ".tx: " & character'val(i); -- print ASCII
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end if;
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if (i = 10) then -- Linux line break
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writeline(file_uart_tx_out, l);
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elsif (i /= 13) then -- Remove additional carriage return
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write(l, character'val(i));
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end if;
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else
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uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
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uart_rx_bitcnt <= uart_rx_bitcnt - 1;
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end if;
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else
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uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
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end if;
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end if;
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end if;
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end process uart_rx_console;
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end architecture;
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