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[rtl] code cleanups
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stnolting
parent
c802b58f2d
commit
a87d1df087
2 changed files with 71 additions and 82 deletions
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@ -140,23 +140,23 @@ begin
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-- -------------------------------------------------------------------------------------------
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-- CPU ISA configuration --
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assert false report
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"NEORV32 CPU Configuration: RV32" &
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cond_sel_string_f(CPU_EXTENSION_RISCV_E, "E", "I") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_A, "A", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_B, "B", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "" ) &
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cond_sel_string_f(true, "_Zicsr", "" ) & -- always enabled
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "" ) &
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cond_sel_string_f(true, "_Zifencei", "" ) & -- always enabled
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext, "_Sdext", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Sdtrig, "_Sdtrig", "" ) &
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cond_sel_string_f(pmp_enable_c, "_Smpmp", "" )
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"NEORV32 CPU Configuration: rv32" &
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cond_sel_string_f(CPU_EXTENSION_RISCV_E, "e", "i") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_M, "m", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_A, "a", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_C, "c", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_B, "b", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_U, "u", "" ) &
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cond_sel_string_f(true, "_zicsr", "" ) & -- always enabled
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_zicntr", "" ) &
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cond_sel_string_f(true, "_zifencei", "" ) & -- always enabled
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_zfinx", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_zihpm", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_zmmul", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_zxcfu", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext, "_sdext", "" ) &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Sdtrig, "_sdtrig", "" ) &
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cond_sel_string_f(pmp_enable_c, "_smpmp", "" )
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severity note;
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-- simulation notifier --
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@ -76,7 +76,6 @@ architecture neorv32_fifo_rtl of neorv32_fifo is
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w_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- write pointer
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r_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- read pointer
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data : fifo_data_t; -- fifo memory
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buf : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- if single-entry FIFO
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match : std_ulogic;
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empty : std_ulogic;
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full : std_ulogic;
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@ -120,9 +119,6 @@ begin
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end if;
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end process pointer_update;
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-- FIFO Status ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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check_large:
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if (fifo_depth_c > 1) generate
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fifo.match <= '1' when (fifo.r_pnt(fifo.r_pnt'left-1 downto 0) = fifo.w_pnt(fifo.w_pnt'left-1 downto 0)) else '0';
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@ -144,17 +140,68 @@ begin
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fifo.avail <= not fifo.empty;
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-- Status Output --------------------------------------------------------------------------
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-- FIFO Write -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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status_async: -- asynchronous
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fifo_memory: -- real FIFO memory (several entries)
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if (fifo_depth_c > 1) generate
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sync_read: process(clk_i)
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begin
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if rising_edge(clk_i) then -- no reset to infer block RAM
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if (fifo.we = '1') then
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fifo.data(to_integer(unsigned(fifo.w_pnt(fifo.w_pnt'left-1 downto 0)))) <= wdata_i;
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end if;
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end if;
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end process sync_read;
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end generate;
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fifo_buffer: -- simple register (single entry)
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if (fifo_depth_c = 1) generate
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sync_read: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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fifo.data(0) <= (others => '0');
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elsif rising_edge(clk_i) then
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if (fifo.we = '1') then
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fifo.data(0) <= wdata_i;
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end if;
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end if;
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end process sync_read;
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end generate;
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-- FIFO Read ------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fifo_read_async: -- asynchronous read
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if (FIFO_RSYNC = false) generate
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async_read: process(fifo)
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begin
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if (fifo_depth_c = 1) then
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rdata_o <= fifo.data(0);
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else
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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end if;
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end process async_read;
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-- status --
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free_o <= fifo.free;
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avail_o <= fifo.avail;
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half_o <= fifo.half;
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end generate;
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status_sync: -- synchronous
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fifo_read_sync: -- synchronous read
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if (FIFO_RSYNC = true) generate
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async_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (fifo_depth_c = 1) then
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rdata_o <= fifo.data(0);
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else
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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end if;
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end if;
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end process async_read;
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-- status --
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sync_status_flags: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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@ -170,62 +217,4 @@ begin
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end generate;
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-- FIFO Memory - Write --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fifo_memory: -- real FIFO memory (several entries)
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if (fifo_depth_c > 1) generate
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sync_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (fifo.we = '1') then
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fifo.data(to_integer(unsigned(fifo.w_pnt(fifo.w_pnt'left-1 downto 0)))) <= wdata_i;
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end if;
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end if;
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end process sync_read;
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fifo.buf <= (others => '0'); -- unused
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end generate;
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fifo_buffer: -- simple register (single entry)
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if (fifo_depth_c = 1) generate
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sync_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (fifo.we = '1') then
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fifo.buf <= wdata_i;
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end if;
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end if;
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end process sync_read;
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fifo.data <= (others => (others => '0')); -- unused
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end generate;
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-- FIFO Memory - Read ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fifo_read_async: -- "asynchronous" read
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if (FIFO_RSYNC = false) generate
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async_read: process(fifo)
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begin
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if (fifo_depth_c = 1) then
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rdata_o <= fifo.buf;
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else
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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end if;
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end process async_read;
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end generate;
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fifo_read_sync: -- synchronous read
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if (FIFO_RSYNC = true) generate
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async_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (fifo_depth_c = 1) then
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rdata_o <= fifo.buf;
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else
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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end if;
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end if;
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end process async_read;
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end generate;
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end neorv32_fifo_rtl;
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